Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 11:56:22 -07:00
|
|
|
using ARMeilleure.IntermediateRepresentation;
|
|
|
|
using ARMeilleure.Translation;
|
|
|
|
using System;
|
|
|
|
using System.Collections.Generic;
|
|
|
|
using System.Text;
|
|
|
|
|
|
|
|
namespace ARMeilleure.Diagnostics
|
|
|
|
{
|
|
|
|
static class IRDumper
|
|
|
|
{
|
|
|
|
private const string Indentation = " ";
|
|
|
|
|
|
|
|
public static string GetDump(ControlFlowGraph cfg)
|
|
|
|
{
|
|
|
|
StringBuilder sb = new StringBuilder();
|
|
|
|
|
|
|
|
Dictionary<Operand, string> localNames = new Dictionary<Operand, string>();
|
|
|
|
|
|
|
|
string indentation = string.Empty;
|
|
|
|
|
|
|
|
void IncreaseIndentation()
|
|
|
|
{
|
|
|
|
indentation += Indentation;
|
|
|
|
}
|
|
|
|
|
|
|
|
void DecreaseIndentation()
|
|
|
|
{
|
|
|
|
indentation = indentation.Substring(0, indentation.Length - Indentation.Length);
|
|
|
|
}
|
|
|
|
|
|
|
|
void AppendLine(string text)
|
|
|
|
{
|
|
|
|
sb.AppendLine(indentation + text);
|
|
|
|
}
|
|
|
|
|
|
|
|
IncreaseIndentation();
|
|
|
|
|
2020-02-17 13:30:54 -08:00
|
|
|
for (BasicBlock block = cfg.Blocks.First; block != null; block = block.ListNext)
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 11:56:22 -07:00
|
|
|
{
|
|
|
|
string blockName = GetBlockName(block);
|
|
|
|
|
|
|
|
if (block.Next != null)
|
|
|
|
{
|
|
|
|
blockName += $" (next {GetBlockName(block.Next)})";
|
|
|
|
}
|
|
|
|
|
|
|
|
if (block.Branch != null)
|
|
|
|
{
|
|
|
|
blockName += $" (branch {GetBlockName(block.Branch)})";
|
|
|
|
}
|
|
|
|
|
|
|
|
blockName += ":";
|
|
|
|
|
|
|
|
AppendLine(blockName);
|
|
|
|
|
|
|
|
IncreaseIndentation();
|
|
|
|
|
2020-02-17 13:30:54 -08:00
|
|
|
for (Node node = block.Operations.First; node != null; node = node.ListNext)
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 11:56:22 -07:00
|
|
|
{
|
|
|
|
string[] sources = new string[node.SourcesCount];
|
|
|
|
|
|
|
|
string instName = string.Empty;
|
|
|
|
|
|
|
|
if (node is PhiNode phi)
|
|
|
|
{
|
|
|
|
for (int index = 0; index < sources.Length; index++)
|
|
|
|
{
|
|
|
|
string phiBlockName = GetBlockName(phi.GetBlock(index));
|
|
|
|
|
|
|
|
string operName = GetOperandName(phi.GetSource(index), localNames);
|
|
|
|
|
|
|
|
sources[index] = $"({phiBlockName}: {operName})";
|
|
|
|
}
|
|
|
|
|
|
|
|
instName = "Phi";
|
|
|
|
}
|
|
|
|
else if (node is Operation operation)
|
|
|
|
{
|
|
|
|
for (int index = 0; index < sources.Length; index++)
|
|
|
|
{
|
|
|
|
sources[index] = GetOperandName(operation.GetSource(index), localNames);
|
|
|
|
}
|
|
|
|
|
|
|
|
instName = operation.Instruction.ToString();
|
|
|
|
}
|
|
|
|
|
|
|
|
string allSources = string.Join(", ", sources);
|
|
|
|
|
|
|
|
string line = instName + " " + allSources;
|
|
|
|
|
|
|
|
if (node.Destination != null)
|
|
|
|
{
|
|
|
|
line = GetOperandName(node.Destination, localNames) + " = " + line;
|
|
|
|
}
|
|
|
|
|
|
|
|
AppendLine(line);
|
|
|
|
}
|
|
|
|
|
|
|
|
DecreaseIndentation();
|
|
|
|
}
|
|
|
|
|
|
|
|
return sb.ToString();
|
|
|
|
}
|
|
|
|
|
|
|
|
private static string GetBlockName(BasicBlock block)
|
|
|
|
{
|
|
|
|
return $"block{block.Index}";
|
|
|
|
}
|
|
|
|
|
|
|
|
private static string GetOperandName(Operand operand, Dictionary<Operand, string> localNames)
|
|
|
|
{
|
|
|
|
if (operand == null)
|
|
|
|
{
|
|
|
|
return "<NULL>";
|
|
|
|
}
|
|
|
|
|
|
|
|
string name = string.Empty;
|
|
|
|
|
|
|
|
if (operand.Kind == OperandKind.LocalVariable)
|
|
|
|
{
|
|
|
|
if (!localNames.TryGetValue(operand, out string localName))
|
|
|
|
{
|
|
|
|
localName = "%" + localNames.Count;
|
|
|
|
|
|
|
|
localNames.Add(operand, localName);
|
|
|
|
}
|
|
|
|
|
|
|
|
name = localName;
|
|
|
|
}
|
|
|
|
else if (operand.Kind == OperandKind.Register)
|
|
|
|
{
|
|
|
|
Register reg = operand.GetRegister();
|
|
|
|
|
|
|
|
switch (reg.Type)
|
|
|
|
{
|
|
|
|
case RegisterType.Flag: name = "b" + reg.Index; break;
|
|
|
|
case RegisterType.Integer: name = "r" + reg.Index; break;
|
|
|
|
case RegisterType.Vector: name = "v" + reg.Index; break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else if (operand.Kind == OperandKind.Constant)
|
|
|
|
{
|
|
|
|
name = "0x" + operand.Value.ToString("X");
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
name = operand.Kind.ToString().ToLower();
|
|
|
|
}
|
|
|
|
|
|
|
|
return GetTypeName(operand.Type) + " " + name;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static string GetTypeName(OperandType type)
|
|
|
|
{
|
|
|
|
switch (type)
|
|
|
|
{
|
|
|
|
case OperandType.FP32: return "f32";
|
|
|
|
case OperandType.FP64: return "f64";
|
|
|
|
case OperandType.I32: return "i32";
|
|
|
|
case OperandType.I64: return "i64";
|
|
|
|
case OperandType.None: return "none";
|
|
|
|
case OperandType.V128: return "v128";
|
|
|
|
}
|
|
|
|
|
|
|
|
throw new ArgumentException($"Invalid operand type \"{type}\".");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|