2018-02-25 17:14:58 -08:00
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using ChocolArm64.Events;
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2019-02-04 13:26:05 -08:00
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using ChocolArm64.Translation;
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2018-02-04 15:08:20 -08:00
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using System;
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2018-03-13 17:24:17 -07:00
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using System.Diagnostics;
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2018-09-19 08:16:20 -07:00
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using System.Runtime.CompilerServices;
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2018-05-11 16:10:27 -07:00
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using System.Runtime.Intrinsics;
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2018-02-04 15:08:20 -08:00
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namespace ChocolArm64.State
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{
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2018-10-30 18:43:02 -07:00
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public class CpuThreadState
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{
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internal const int ErgSizeLog2 = 4;
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internal const int DczSizeLog2 = 4;
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2018-09-19 08:16:20 -07:00
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private const int MinInstForCheck = 4000000;
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2018-02-04 15:08:20 -08:00
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public ulong X0, X1, X2, X3, X4, X5, X6, X7,
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X8, X9, X10, X11, X12, X13, X14, X15,
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X16, X17, X18, X19, X20, X21, X22, X23,
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X24, X25, X26, X27, X28, X29, X30, X31;
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2018-05-11 16:10:27 -07:00
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public Vector128<float> V0, V1, V2, V3, V4, V5, V6, V7,
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V8, V9, V10, V11, V12, V13, V14, V15,
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V16, V17, V18, V19, V20, V21, V22, V23,
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V24, V25, V26, V27, V28, V29, V30, V31;
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2018-02-04 15:08:20 -08:00
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Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)
* Rename some opcode classes and flag masks for consistency
* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations
* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC
* Re-align arm32 instructions on the opcode table
2019-01-29 08:06:11 -08:00
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public bool Aarch32;
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public bool Thumb;
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public bool BigEndian;
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public bool Overflow;
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public bool Carry;
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public bool Zero;
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public bool Negative;
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2019-01-24 17:59:53 -08:00
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public int ElrHyp;
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2018-03-11 21:04:52 -07:00
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public bool Running { get; set; }
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public int Core { get; set; }
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private bool _interrupted;
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private int _syncCount;
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public long TpidrEl0 { get; set; }
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public long Tpidr { get; set; }
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public int Fpcr { get; set; }
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public int Fpsr { get; set; }
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public int Psr
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{
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get
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{
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Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)
* Rename some opcode classes and flag masks for consistency
* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations
* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC
* Re-align arm32 instructions on the opcode table
2019-01-29 08:06:11 -08:00
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return (Negative ? (int)PState.NMask : 0) |
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(Zero ? (int)PState.ZMask : 0) |
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(Carry ? (int)PState.CMask : 0) |
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(Overflow ? (int)PState.VMask : 0);
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}
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}
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public uint CtrEl0 => 0x8444c004;
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public uint DczidEl0 => 0x00000004;
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public ulong CntfrqEl0 { get; set; }
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public ulong CntpctEl0
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{
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get
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{
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double ticks = _tickCounter.ElapsedTicks * _hostTickFreq;
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return (ulong)(ticks * CntfrqEl0);
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}
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}
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public event EventHandler<EventArgs> Interrupt;
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public event EventHandler<InstExceptionEventArgs> Break;
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public event EventHandler<InstExceptionEventArgs> SvcCall;
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public event EventHandler<InstUndefinedEventArgs> Undefined;
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2018-02-10 05:24:16 -08:00
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2018-10-30 18:43:02 -07:00
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private static Stopwatch _tickCounter;
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private static double _hostTickFreq;
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internal Translator CurrentTranslator;
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static CpuThreadState()
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{
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_hostTickFreq = 1.0 / Stopwatch.Frequency;
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_tickCounter = new Stopwatch();
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_tickCounter.Start();
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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internal bool Synchronize(int bbWeight)
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{
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//Firing a interrupt frequently is expensive, so we only
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//do it after a given number of instructions has executed.
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_syncCount += bbWeight;
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if (_syncCount >= MinInstForCheck)
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{
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CheckInterrupt();
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}
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2018-08-16 16:47:36 -07:00
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return Running;
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}
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2018-09-18 16:36:43 -07:00
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internal void RequestInterrupt()
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{
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_interrupted = true;
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}
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[MethodImpl(MethodImplOptions.NoInlining)]
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private void CheckInterrupt()
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{
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_syncCount = 0;
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if (_interrupted)
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{
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_interrupted = false;
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Interrupt?.Invoke(this, EventArgs.Empty);
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}
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}
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internal void OnBreak(long position, int imm)
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{
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Break?.Invoke(this, new InstExceptionEventArgs(position, imm));
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}
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internal void OnSvcCall(long position, int imm)
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{
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SvcCall?.Invoke(this, new InstExceptionEventArgs(position, imm));
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}
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internal void OnUndefined(long position, int rawOpCode)
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{
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Undefined?.Invoke(this, new InstUndefinedEventArgs(position, rawOpCode));
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}
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2019-01-24 17:59:53 -08:00
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internal ExecutionMode GetExecutionMode()
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{
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Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)
* Rename some opcode classes and flag masks for consistency
* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations
* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC
* Re-align arm32 instructions on the opcode table
2019-01-29 08:06:11 -08:00
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if (!Aarch32)
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{
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return ExecutionMode.Aarch64;
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}
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else
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{
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return Thumb ? ExecutionMode.Aarch32Thumb : ExecutionMode.Aarch32Arm;
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}
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}
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internal bool GetFpcrFlag(Fpcr flag)
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{
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return (Fpcr & (1 << (int)flag)) != 0;
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}
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2018-10-30 18:43:02 -07:00
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internal void SetFpsrFlag(Fpsr flag)
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{
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Fpsr |= 1 << (int)flag;
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}
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internal RoundMode FPRoundingMode()
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{
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return (RoundMode)((Fpcr >> (int)State.Fpcr.RMode) & 3);
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}
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}
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}
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