2018-02-23 04:29:20 -08:00
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using ChocolArm64;
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2018-02-15 16:04:38 -08:00
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using ChocolArm64.Memory;
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using ChocolArm64.State;
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2018-06-18 10:55:26 -07:00
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2018-02-15 16:04:38 -08:00
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using NUnit.Framework;
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2018-06-18 10:55:26 -07:00
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2018-05-11 16:10:27 -07:00
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using System;
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using System.Runtime.Intrinsics;
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using System.Runtime.Intrinsics.X86;
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2018-06-10 17:46:42 -07:00
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using System.Threading;
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2018-02-15 16:04:38 -08:00
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namespace Ryujinx.Tests.Cpu
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{
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[TestFixture]
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2018-02-23 04:29:20 -08:00
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public class CpuTest
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{
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protected long Position { get; private set; }
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private long Size;
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private long EntryPoint;
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private AMemory Memory;
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private AThread Thread;
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2018-02-15 16:04:38 -08:00
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[SetUp]
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public void Setup()
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{
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2018-02-23 04:29:20 -08:00
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Position = 0x0;
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Size = 0x1000;
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EntryPoint = Position;
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2018-02-25 17:14:58 -08:00
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ATranslator Translator = new ATranslator();
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2018-03-09 18:12:57 -08:00
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Memory = new AMemory();
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2018-02-27 15:45:07 -08:00
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Memory.Manager.Map(Position, Size, 2, AMemoryPerm.Read | AMemoryPerm.Write | AMemoryPerm.Execute);
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2018-03-11 21:04:52 -07:00
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Thread = new AThread(Translator, Memory, EntryPoint);
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2018-02-15 16:04:38 -08:00
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}
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[TearDown]
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public void Teardown()
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{
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Memory.Dispose();
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Memory = null;
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Thread = null;
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}
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2018-02-23 04:29:20 -08:00
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protected void Reset()
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{
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Teardown();
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Setup();
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}
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protected void Opcode(uint Opcode)
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{
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Thread.Memory.WriteUInt32Unchecked(Position, Opcode);
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Position += 4;
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}
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2018-04-18 13:22:45 -07:00
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protected void SetThreadState(ulong X0 = 0, ulong X1 = 0, ulong X2 = 0, ulong X3 = 0, ulong X31 = 0,
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Vector128<float> V0 = default(Vector128<float>),
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Vector128<float> V1 = default(Vector128<float>),
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Vector128<float> V2 = default(Vector128<float>),
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bool Overflow = false, bool Carry = false, bool Zero = false, bool Negative = false,
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int Fpcr = 0x0, int Fpsr = 0x0)
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{
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Thread.ThreadState.X0 = X0;
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Thread.ThreadState.X1 = X1;
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Thread.ThreadState.X2 = X2;
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Thread.ThreadState.X3 = X3;
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Thread.ThreadState.X31 = X31;
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Thread.ThreadState.V0 = V0;
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Thread.ThreadState.V1 = V1;
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Thread.ThreadState.V2 = V2;
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2018-02-23 06:53:32 -08:00
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Thread.ThreadState.Overflow = Overflow;
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Thread.ThreadState.Carry = Carry;
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Thread.ThreadState.Zero = Zero;
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Thread.ThreadState.Negative = Negative;
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2018-03-05 04:21:19 -08:00
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Thread.ThreadState.Fpcr = Fpcr;
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Thread.ThreadState.Fpsr = Fpsr;
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}
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protected void ExecuteOpcodes()
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{
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using (ManualResetEvent Wait = new ManualResetEvent(false))
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{
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Thread.ThreadState.Break += (sender, e) => Thread.StopExecution();
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Thread.WorkFinished += (sender, e) => Wait.Set();
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Thread.Execute();
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Wait.WaitOne();
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}
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}
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protected AThreadState GetThreadState()
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{
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return Thread.ThreadState;
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}
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2018-02-23 04:29:20 -08:00
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protected AThreadState SingleOpcode(uint Opcode,
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ulong X0 = 0, ulong X1 = 0, ulong X2 = 0, ulong X3 = 0, ulong X31 = 0,
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2018-05-11 16:10:27 -07:00
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Vector128<float> V0 = default(Vector128<float>),
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Vector128<float> V1 = default(Vector128<float>),
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Vector128<float> V2 = default(Vector128<float>),
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2018-04-29 16:39:58 -07:00
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bool Overflow = false, bool Carry = false, bool Zero = false, bool Negative = false,
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int Fpcr = 0x0, int Fpsr = 0x0)
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{
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this.Opcode(Opcode);
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this.Opcode(0xD4200000); // BRK #0
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this.Opcode(0xD65F03C0); // RET
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2018-04-29 16:39:58 -07:00
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SetThreadState(X0, X1, X2, X3, X31, V0, V1, V2, Overflow, Carry, Zero, Negative, Fpcr, Fpsr);
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2018-02-23 04:29:20 -08:00
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ExecuteOpcodes();
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return GetThreadState();
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2018-02-15 16:04:38 -08:00
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}
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2018-05-11 16:10:27 -07:00
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2018-06-30 08:40:41 -07:00
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protected static Vector128<float> MakeVectorE0(double E0)
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{
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2018-06-30 08:40:41 -07:00
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return Sse.StaticCast<long, float>(Sse2.SetVector128(0, BitConverter.DoubleToInt64Bits(E0)));
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Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-25 18:32:29 -07:00
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}
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2018-05-11 16:10:27 -07:00
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2018-06-30 08:40:41 -07:00
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protected static Vector128<float> MakeVectorE0E1(double E0, double E1)
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Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-25 18:32:29 -07:00
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{
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2018-06-30 08:40:41 -07:00
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return Sse.StaticCast<long, float>(Sse2.SetVector128(BitConverter.DoubleToInt64Bits(E1),
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BitConverter.DoubleToInt64Bits(E0)));
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Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-25 18:32:29 -07:00
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}
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2018-06-30 08:40:41 -07:00
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protected static Vector128<float> MakeVectorE1(double E1)
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Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-25 18:32:29 -07:00
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{
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2018-06-30 08:40:41 -07:00
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return Sse.StaticCast<long, float>(Sse2.SetVector128(BitConverter.DoubleToInt64Bits(E1), 0));
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2018-05-11 16:10:27 -07:00
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}
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Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-25 18:32:29 -07:00
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protected static double VectorExtractDouble(Vector128<float> Vector, byte Index)
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2018-05-11 16:10:27 -07:00
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{
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Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-25 18:32:29 -07:00
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long Value = Sse41.Extract(Sse.StaticCast<float, long>(Vector), Index);
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return BitConverter.Int64BitsToDouble(Value);
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2018-05-11 16:10:27 -07:00
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}
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2018-06-30 08:40:41 -07:00
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protected static Vector128<float> MakeVectorE0(ulong E0)
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2018-05-11 16:10:27 -07:00
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{
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2018-06-30 08:40:41 -07:00
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return Sse.StaticCast<ulong, float>(Sse2.SetVector128(0, E0));
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2018-05-11 16:10:27 -07:00
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}
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2018-06-30 08:40:41 -07:00
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protected static Vector128<float> MakeVectorE0E1(ulong E0, ulong E1)
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2018-05-11 16:10:27 -07:00
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{
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2018-06-30 08:40:41 -07:00
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return Sse.StaticCast<ulong, float>(Sse2.SetVector128(E1, E0));
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2018-05-11 16:10:27 -07:00
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}
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2018-06-30 08:40:41 -07:00
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protected static Vector128<float> MakeVectorE1(ulong E1)
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2018-05-11 16:10:27 -07:00
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{
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2018-06-30 08:40:41 -07:00
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return Sse.StaticCast<ulong, float>(Sse2.SetVector128(E1, 0));
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2018-05-11 16:10:27 -07:00
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}
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protected static ulong GetVectorE0(Vector128<float> Vector)
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{
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2018-06-30 08:40:41 -07:00
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return Sse41.Extract(Sse.StaticCast<float, ulong>(Vector), (byte)0);
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2018-05-11 16:10:27 -07:00
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}
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protected static ulong GetVectorE1(Vector128<float> Vector)
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{
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2018-06-30 08:40:41 -07:00
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return Sse41.Extract(Sse.StaticCast<float, ulong>(Vector), (byte)1);
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2018-05-11 16:10:27 -07:00
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}
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2018-02-15 16:04:38 -08:00
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}
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}
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