Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 11:56:22 -07:00
|
|
|
using ARMeilleure.Memory;
|
|
|
|
using ARMeilleure.State;
|
2018-11-28 14:18:09 -08:00
|
|
|
using Ryujinx.HLE.HOS.Diagnostics.Demangler;
|
2018-12-17 21:33:36 -08:00
|
|
|
using Ryujinx.HLE.HOS.Kernel.Memory;
|
2018-11-28 14:18:09 -08:00
|
|
|
using Ryujinx.HLE.Loaders.Elf;
|
|
|
|
using System.Collections.Generic;
|
|
|
|
using System.Linq;
|
|
|
|
using System.Text;
|
|
|
|
using System.Threading;
|
|
|
|
|
2018-12-17 21:33:36 -08:00
|
|
|
namespace Ryujinx.HLE.HOS.Kernel.Process
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
|
|
|
class HleProcessDebugger
|
|
|
|
{
|
|
|
|
private const int Mod0 = 'M' << 0 | 'O' << 8 | 'D' << 16 | '0' << 24;
|
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
private KProcess _owner;
|
2018-11-28 14:18:09 -08:00
|
|
|
|
|
|
|
private class Image
|
|
|
|
{
|
2018-12-04 16:52:39 -08:00
|
|
|
public long BaseAddress { get; private set; }
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-04 16:52:39 -08:00
|
|
|
public ElfSymbol[] Symbols { get; private set; }
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
public Image(long baseAddress, ElfSymbol[] symbols)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
BaseAddress = baseAddress;
|
|
|
|
Symbols = symbols;
|
2018-11-28 14:18:09 -08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
private List<Image> _images;
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
private int _loaded;
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
public HleProcessDebugger(KProcess owner)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
_owner = owner;
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
_images = new List<Image>();
|
2018-11-28 14:18:09 -08:00
|
|
|
}
|
|
|
|
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 11:56:22 -07:00
|
|
|
public string GetGuestStackTrace(IExecutionContext context)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
|
|
|
EnsureLoaded();
|
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
StringBuilder trace = new StringBuilder();
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
void AppendTrace(long address)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
Image image = GetImage(address, out int imageIndex);
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
if (image == null || !TryGetSubName(image, address, out string subName))
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
subName = $"Sub{address:x16}";
|
2018-11-28 14:18:09 -08:00
|
|
|
}
|
2018-12-06 03:16:24 -08:00
|
|
|
else if (subName.StartsWith("_Z"))
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
subName = Demangler.Parse(subName);
|
2018-11-28 14:18:09 -08:00
|
|
|
}
|
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
if (image != null)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
long offset = address - image.BaseAddress;
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
string imageName = GetGuessedNsoNameFromIndex(imageIndex);
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2019-03-14 20:37:54 -07:00
|
|
|
trace.AppendLine($" {imageName}:0x{offset:x8} {subName}");
|
2018-11-28 14:18:09 -08:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2019-03-14 20:37:54 -07:00
|
|
|
trace.AppendLine($" ??? {subName}");
|
2018-11-28 14:18:09 -08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-07-01 19:39:22 -07:00
|
|
|
// TODO: ARM32.
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 11:56:22 -07:00
|
|
|
long framePointer = (long)context.GetX(29);
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2019-03-14 20:37:54 -07:00
|
|
|
trace.AppendLine($"Process: {_owner.Name}, PID: {_owner.Pid}");
|
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
while (framePointer != 0)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2019-03-14 20:37:54 -07:00
|
|
|
if ((framePointer & 7) != 0 ||
|
2018-12-06 03:16:24 -08:00
|
|
|
!_owner.CpuMemory.IsMapped(framePointer) ||
|
|
|
|
!_owner.CpuMemory.IsMapped(framePointer + 8))
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2019-07-01 19:39:22 -07:00
|
|
|
// Note: This is the return address, we need to subtract one instruction
|
|
|
|
// worth of bytes to get the branch instruction address.
|
2018-12-06 03:16:24 -08:00
|
|
|
AppendTrace(_owner.CpuMemory.ReadInt64(framePointer + 8) - 4);
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
framePointer = _owner.CpuMemory.ReadInt64(framePointer);
|
2018-11-28 14:18:09 -08:00
|
|
|
}
|
|
|
|
|
2019-03-14 20:37:54 -07:00
|
|
|
return trace.ToString();
|
2018-11-28 14:18:09 -08:00
|
|
|
}
|
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
private bool TryGetSubName(Image image, long address, out string name)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
address -= image.BaseAddress;
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
int left = 0;
|
|
|
|
int right = image.Symbols.Length - 1;
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
while (left <= right)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
int size = right - left;
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
int middle = left + (size >> 1);
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
ElfSymbol symbol = image.Symbols[middle];
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
long endAddr = symbol.Value + symbol.Size;
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
if ((ulong)address >= (ulong)symbol.Value && (ulong)address < (ulong)endAddr)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
name = symbol.Name;
|
2018-11-28 14:18:09 -08:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
if ((ulong)address < (ulong)symbol.Value)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
right = middle - 1;
|
2018-11-28 14:18:09 -08:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
left = middle + 1;
|
2018-11-28 14:18:09 -08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
name = null;
|
2018-11-28 14:18:09 -08:00
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
private Image GetImage(long address, out int index)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
lock (_images)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
for (index = _images.Count - 1; index >= 0; index--)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
if ((ulong)address >= (ulong)_images[index].BaseAddress)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
return _images[index];
|
2018-11-28 14:18:09 -08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return null;
|
|
|
|
}
|
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
private string GetGuessedNsoNameFromIndex(int index)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
if ((uint)index > 11)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
|
|
|
return "???";
|
|
|
|
}
|
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
if (index == 0)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
|
|
|
return "rtld";
|
|
|
|
}
|
2018-12-06 03:16:24 -08:00
|
|
|
else if (index == 1)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
|
|
|
return "main";
|
|
|
|
}
|
2018-12-06 03:16:24 -08:00
|
|
|
else if (index == GetImagesCount() - 1)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
|
|
|
return "sdk";
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
return "subsdk" + (index - 2);
|
2018-11-28 14:18:09 -08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
private int GetImagesCount()
|
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
lock (_images)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
return _images.Count;
|
2018-11-28 14:18:09 -08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
private void EnsureLoaded()
|
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
if (Interlocked.CompareExchange(ref _loaded, 1, 0) == 0)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
|
|
|
ScanMemoryForTextSegments();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
private void ScanMemoryForTextSegments()
|
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
ulong oldAddress = 0;
|
|
|
|
ulong address = 0;
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
while (address >= oldAddress)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
KMemoryInfo info = _owner.MemoryManager.QueryMemory(address);
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
if (info.State == MemoryState.Reserved)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
if (info.State == MemoryState.CodeStatic && info.Permission == MemoryPermission.ReadAndExecute)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
LoadMod0Symbols(_owner.CpuMemory, (long)info.Address);
|
2018-11-28 14:18:09 -08:00
|
|
|
}
|
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
oldAddress = address;
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
address = info.Address + info.Size;
|
2018-11-28 14:18:09 -08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 11:56:22 -07:00
|
|
|
private void LoadMod0Symbols(IMemoryManager memory, long textOffset)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
long mod0Offset = textOffset + memory.ReadUInt32(textOffset + 4);
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
if (mod0Offset < textOffset || !memory.IsMapped(mod0Offset) || (mod0Offset & 3) != 0)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
Dictionary<ElfDynamicTag, long> dynamic = new Dictionary<ElfDynamicTag, long>();
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
int mod0Magic = memory.ReadInt32(mod0Offset + 0x0);
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
if (mod0Magic != Mod0)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
long dynamicOffset = memory.ReadInt32(mod0Offset + 0x4) + mod0Offset;
|
|
|
|
long bssStartOffset = memory.ReadInt32(mod0Offset + 0x8) + mod0Offset;
|
|
|
|
long bssEndOffset = memory.ReadInt32(mod0Offset + 0xc) + mod0Offset;
|
|
|
|
long ehHdrStartOffset = memory.ReadInt32(mod0Offset + 0x10) + mod0Offset;
|
|
|
|
long ehHdrEndOffset = memory.ReadInt32(mod0Offset + 0x14) + mod0Offset;
|
|
|
|
long modObjOffset = memory.ReadInt32(mod0Offset + 0x18) + mod0Offset;
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2019-07-01 19:39:22 -07:00
|
|
|
// TODO: Elf32.
|
2018-11-28 14:18:09 -08:00
|
|
|
while (true)
|
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
long tagVal = memory.ReadInt64(dynamicOffset + 0);
|
|
|
|
long value = memory.ReadInt64(dynamicOffset + 8);
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
dynamicOffset += 0x10;
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
ElfDynamicTag tag = (ElfDynamicTag)tagVal;
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
if (tag == ElfDynamicTag.DT_NULL)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
dynamic[tag] = value;
|
2018-11-28 14:18:09 -08:00
|
|
|
}
|
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
if (!dynamic.TryGetValue(ElfDynamicTag.DT_STRTAB, out long strTab) ||
|
|
|
|
!dynamic.TryGetValue(ElfDynamicTag.DT_SYMTAB, out long symTab) ||
|
|
|
|
!dynamic.TryGetValue(ElfDynamicTag.DT_SYMENT, out long symEntSize))
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
long strTblAddr = textOffset + strTab;
|
|
|
|
long symTblAddr = textOffset + symTab;
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
List<ElfSymbol> symbols = new List<ElfSymbol>();
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
while ((ulong)symTblAddr < (ulong)strTblAddr)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
ElfSymbol sym = GetSymbol(memory, symTblAddr, strTblAddr);
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
symbols.Add(sym);
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
symTblAddr += symEntSize;
|
2018-11-28 14:18:09 -08:00
|
|
|
}
|
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
lock (_images)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
_images.Add(new Image(textOffset, symbols.OrderBy(x => x.Value).ToArray()));
|
2018-11-28 14:18:09 -08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 11:56:22 -07:00
|
|
|
private ElfSymbol GetSymbol(IMemoryManager memory, long address, long strTblAddr)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
int nameIndex = memory.ReadInt32(address + 0);
|
|
|
|
int info = memory.ReadByte (address + 4);
|
|
|
|
int other = memory.ReadByte (address + 5);
|
|
|
|
int shIdx = memory.ReadInt16(address + 6);
|
|
|
|
long value = memory.ReadInt64(address + 8);
|
|
|
|
long size = memory.ReadInt64(address + 16);
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
string name = string.Empty;
|
2018-11-28 14:18:09 -08:00
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
for (int chr; (chr = memory.ReadByte(strTblAddr + nameIndex++)) != 0;)
|
2018-11-28 14:18:09 -08:00
|
|
|
{
|
2018-12-06 03:16:24 -08:00
|
|
|
name += (char)chr;
|
2018-11-28 14:18:09 -08:00
|
|
|
}
|
|
|
|
|
2018-12-06 03:16:24 -08:00
|
|
|
return new ElfSymbol(name, info, other, shIdx, value, size);
|
2018-11-28 14:18:09 -08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|