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Ryujinx/ARMeilleure/Instructions/DelegateTypes.cs

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Add a new JIT compiler for CPU code (#693) * Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 11:56:22 -07:00
using ARMeilleure.State;
using System;
namespace ARMeilleure.Instructions
{
delegate double _F64_F64(double a1);
delegate double _F64_F64_F64(double a1, double a2);
delegate double _F64_F64_F64_F64(double a1, double a2, double a3);
delegate double _F64_F64_MidpointRounding(double a1, MidpointRounding a2);
delegate float _F32_F32(float a1);
delegate float _F32_F32_F32(float a1, float a2);
delegate float _F32_F32_F32_F32(float a1, float a2, float a3);
delegate float _F32_F32_MidpointRounding(float a1, MidpointRounding a2);
delegate float _F32_U16(ushort a1);
delegate int _S32_F32(float a1);
delegate int _S32_F32_F32_Bool(float a1, float a2, bool a3);
delegate int _S32_F64(double a1);
delegate int _S32_F64_F64_Bool(double a1, double a2, bool a3);
delegate int _S32_U64_U16(ulong a1, ushort a2);
delegate int _S32_U64_U32(ulong a1, uint a2);
delegate int _S32_U64_U64(ulong a1, ulong a2);
delegate int _S32_U64_U8(ulong a1, byte a2);
delegate int _S32_U64_V128(ulong a1, V128 a2);
delegate long _S64_F32(float a1);
delegate long _S64_F64(double a1);
delegate long _S64_S64(long a1);
delegate long _S64_S64_S32(long a1, int a2);
delegate long _S64_S64_S64(long a1, long a2);
delegate long _S64_S64_S64_Bool_S32(long a1, long a2, bool a3, int a4);
delegate long _S64_S64_S64_S32(long a1, long a2, int a3);
delegate long _S64_U64_S32(ulong a1, int a2);
delegate long _S64_U64_S64(ulong a1, long a2);
delegate ushort _U16_F32(float a1);
delegate ushort _U16_U64(ulong a1);
delegate uint _U32_F32(float a1);
delegate uint _U32_F64(double a1);
delegate uint _U32_U32(uint a1);
delegate uint _U32_U32_U16(uint a1, ushort a2);
delegate uint _U32_U32_U32(uint a1, uint a2);
delegate uint _U32_U32_U64(uint a1, ulong a2);
delegate uint _U32_U32_U8(uint a1, byte a2);
delegate uint _U32_U64(ulong a1);
delegate ulong _U64();
delegate ulong _U64_F32(float a1);
delegate ulong _U64_F64(double a1);
delegate ulong _U64_S64_S32(long a1, int a2);
delegate ulong _U64_S64_U64(long a1, ulong a2);
delegate ulong _U64_U64(ulong a1);
delegate ulong _U64_U64_S32(ulong a1, int a2);
delegate ulong _U64_U64_S64_S32(ulong a1, long a2, int a3);
delegate ulong _U64_U64_U64(ulong a1, ulong a2);
delegate ulong _U64_U64_U64_Bool_S32(ulong a1, ulong a2, bool a3, int a4);
delegate byte _U8_U64(ulong a1);
delegate V128 _V128_U64(ulong a1);
delegate V128 _V128_V128(V128 a1);
delegate V128 _V128_V128_U32_V128(V128 a1, uint a2, V128 a3);
delegate V128 _V128_V128_V128(V128 a1, V128 a2);
delegate V128 _V128_V128_V128_V128(V128 a1, V128 a2, V128 a3);
delegate V128 _V128_V128_V128_V128_V128(V128 a1, V128 a2, V128 a3, V128 a4);
delegate V128 _V128_V128_V128_V128_V128_V128(V128 a1, V128 a2, V128 a3, V128 a4, V128 a5);
delegate void _Void();
delegate void _Void_U64(ulong a1);
delegate void _Void_U64_S32(ulong a1, int a2);
delegate void _Void_U64_U16(ulong a1, ushort a2);
delegate void _Void_U64_U32(ulong a1, uint a2);
delegate void _Void_U64_U64(ulong a1, ulong a2);
delegate void _Void_U64_U8(ulong a1, byte a2);
delegate void _Void_U64_V128(ulong a1, V128 a2);
}
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