2020-07-16 21:21:40 -07:00
|
|
|
|
namespace ARMeilleure.Decoders
|
|
|
|
|
|
{
|
Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths). (#1577)
* Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths).
No test provided (i.e. draft).
* Ptc InternalVersion = 1577
2020-10-13 13:41:33 -07:00
|
|
|
|
class OpCode32SimdRegWide : OpCode32SimdReg
|
2020-07-16 21:21:40 -07:00
|
|
|
|
{
|
2020-10-21 05:13:44 -07:00
|
|
|
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegWide(inst, address, opCode);
|
|
|
|
|
|
|
2020-07-16 21:21:40 -07:00
|
|
|
|
public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
|
|
|
|
|
{
|
|
|
|
|
|
Q = false;
|
|
|
|
|
|
RegisterSize = RegisterSize.Simd64;
|
|
|
|
|
|
|
|
|
|
|
|
// Subclasses have their own handling of Vx to account for before checking.
|
|
|
|
|
|
if (GetType() == typeof(OpCode32SimdRegWide) && DecoderHelper.VectorArgumentsInvalid(true, Vd, Vn))
|
|
|
|
|
|
{
|
|
|
|
|
|
Instruction = InstDescriptor.Undefined;
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
