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https://github.com/Ryujinx/Ryujinx.git
synced 2025-06-28 23:50:46 -07:00
Implement VMNMX shader instruction (#1032)
* Implement VMNMX shader instruction * No need for the gap on the enum * Fix typo
This commit is contained in:
@ -205,6 +205,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
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Set("1101111101001x", InstEmit.Txq, typeof(OpCodeTex));
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Set("1101111101010x", InstEmit.TxqB, typeof(OpCodeTex));
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Set("01011111xxxxxx", InstEmit.Vmad, typeof(OpCodeVideo));
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Set("0011101xxxxxxx", InstEmit.Vmnmx, typeof(OpCodeVideo));
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Set("0101000011011x", InstEmit.Vote, typeof(OpCodeVote));
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Set("0100111xxxxxxx", InstEmit.Xmad, typeof(OpCodeAluCbuf));
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Set("0011011x00xxxx", InstEmit.Xmad, typeof(OpCodeAluImm));
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@ -6,19 +6,98 @@ namespace Ryujinx.Graphics.Shader.Decoders
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{
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public Register Rd { get; }
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public Register Ra { get; }
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public Register Rb { get; }
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public Register Rc { get; }
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public bool SetCondCode { get; protected set; }
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public bool Saturate { get; protected set; }
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public int Immediate { get; }
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public int RaSelection { get; }
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public int RbSelection { get; }
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public bool SetCondCode { get; }
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public bool HasRb { get; }
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public VideoType RaType { get; }
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public VideoType RbType { get; }
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public VideoPostOp PostOp { get; }
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public bool DstSigned { get; }
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public bool Saturate { get; }
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public OpCodeVideo(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
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{
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Rd = new Register(opCode.Extract(0, 8), RegisterType.Gpr);
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Ra = new Register(opCode.Extract(8, 8), RegisterType.Gpr);
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Rb = new Register(opCode.Extract(20, 8), RegisterType.Gpr);
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Rc = new Register(opCode.Extract(39, 8), RegisterType.Gpr);
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RaSelection = opCode.Extract(36, 2);
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RbSelection = opCode.Extract(28, 2);
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RaType = opCode.Extract(37, 2) switch
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{
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2 => VideoType.U16,
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3 => VideoType.U32,
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_ => VideoType.U8
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};
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RbType = opCode.Extract(29, 2) switch
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{
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2 => VideoType.U16,
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3 => VideoType.U32,
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_ => VideoType.U8
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};
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if (opCode.Extract(48))
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{
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RaType |= VideoType.Signed;
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}
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if (!opCode.Extract(50))
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{
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// Immediate variant.
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Immediate = opCode.Extract(16, 20);
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RbType = opCode.Extract(49) ? VideoType.S16 : VideoType.U16;
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if (RbType == VideoType.S16)
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{
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Immediate = (Immediate << 12) >> 12;
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}
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}
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else if (opCode.Extract(49))
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{
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RbType |= VideoType.Signed;
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}
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if (RaType == VideoType.U16)
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{
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RaSelection &= 1;
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}
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else if (RaType == VideoType.U32)
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{
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RaSelection = 0;
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}
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if (RbType == VideoType.U16)
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{
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RbSelection &= 1;
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}
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else if (RbType == VideoType.U32)
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{
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RbSelection = 0;
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}
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SetCondCode = opCode.Extract(47);
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Saturate = opCode.Extract(55);
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HasRb = opCode.Extract(50);
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PostOp = (VideoPostOp)opCode.Extract(51, 3);
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DstSigned = opCode.Extract(54);
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Saturate = opCode.Extract(55);
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}
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}
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}
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14
Ryujinx.Graphics.Shader/Decoders/VideoPostOp.cs
Normal file
14
Ryujinx.Graphics.Shader/Decoders/VideoPostOp.cs
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@ -0,0 +1,14 @@
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namespace Ryujinx.Graphics.Shader.Decoders
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{
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enum VideoPostOp
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{
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Mrg16h,
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Mrg16l,
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Mrg8b0,
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Mrg8b2,
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Acc,
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Min,
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Max,
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Pass
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}
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}
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15
Ryujinx.Graphics.Shader/Decoders/VideoType.cs
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15
Ryujinx.Graphics.Shader/Decoders/VideoType.cs
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@ -0,0 +1,15 @@
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namespace Ryujinx.Graphics.Shader.Decoders
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{
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enum VideoType
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{
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U8 = 0,
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U16 = 1,
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U32 = 2,
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Signed = 1 << 2,
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S8 = Signed | U8,
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S16 = Signed | U16,
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S32 = Signed | U32
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}
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}
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