Implement VMNMX shader instruction (#1032)

* Implement VMNMX shader instruction

* No need for the gap on the enum

* Fix typo
This commit is contained in:
gdkchan
2020-03-25 11:49:10 -03:00
committed by GitHub
parent 56374c8633
commit 1586450a38
5 changed files with 232 additions and 4 deletions

View File

@ -205,6 +205,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
Set("1101111101001x", InstEmit.Txq, typeof(OpCodeTex));
Set("1101111101010x", InstEmit.TxqB, typeof(OpCodeTex));
Set("01011111xxxxxx", InstEmit.Vmad, typeof(OpCodeVideo));
Set("0011101xxxxxxx", InstEmit.Vmnmx, typeof(OpCodeVideo));
Set("0101000011011x", InstEmit.Vote, typeof(OpCodeVote));
Set("0100111xxxxxxx", InstEmit.Xmad, typeof(OpCodeAluCbuf));
Set("0011011x00xxxx", InstEmit.Xmad, typeof(OpCodeAluImm));

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@ -6,19 +6,98 @@ namespace Ryujinx.Graphics.Shader.Decoders
{
public Register Rd { get; }
public Register Ra { get; }
public Register Rb { get; }
public Register Rc { get; }
public bool SetCondCode { get; protected set; }
public bool Saturate { get; protected set; }
public int Immediate { get; }
public int RaSelection { get; }
public int RbSelection { get; }
public bool SetCondCode { get; }
public bool HasRb { get; }
public VideoType RaType { get; }
public VideoType RbType { get; }
public VideoPostOp PostOp { get; }
public bool DstSigned { get; }
public bool Saturate { get; }
public OpCodeVideo(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
{
Rd = new Register(opCode.Extract(0, 8), RegisterType.Gpr);
Ra = new Register(opCode.Extract(8, 8), RegisterType.Gpr);
Rb = new Register(opCode.Extract(20, 8), RegisterType.Gpr);
Rc = new Register(opCode.Extract(39, 8), RegisterType.Gpr);
RaSelection = opCode.Extract(36, 2);
RbSelection = opCode.Extract(28, 2);
RaType = opCode.Extract(37, 2) switch
{
2 => VideoType.U16,
3 => VideoType.U32,
_ => VideoType.U8
};
RbType = opCode.Extract(29, 2) switch
{
2 => VideoType.U16,
3 => VideoType.U32,
_ => VideoType.U8
};
if (opCode.Extract(48))
{
RaType |= VideoType.Signed;
}
if (!opCode.Extract(50))
{
// Immediate variant.
Immediate = opCode.Extract(16, 20);
RbType = opCode.Extract(49) ? VideoType.S16 : VideoType.U16;
if (RbType == VideoType.S16)
{
Immediate = (Immediate << 12) >> 12;
}
}
else if (opCode.Extract(49))
{
RbType |= VideoType.Signed;
}
if (RaType == VideoType.U16)
{
RaSelection &= 1;
}
else if (RaType == VideoType.U32)
{
RaSelection = 0;
}
if (RbType == VideoType.U16)
{
RbSelection &= 1;
}
else if (RbType == VideoType.U32)
{
RbSelection = 0;
}
SetCondCode = opCode.Extract(47);
Saturate = opCode.Extract(55);
HasRb = opCode.Extract(50);
PostOp = (VideoPostOp)opCode.Extract(51, 3);
DstSigned = opCode.Extract(54);
Saturate = opCode.Extract(55);
}
}
}

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@ -0,0 +1,14 @@
namespace Ryujinx.Graphics.Shader.Decoders
{
enum VideoPostOp
{
Mrg16h,
Mrg16l,
Mrg8b0,
Mrg8b2,
Acc,
Min,
Max,
Pass
}
}

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@ -0,0 +1,15 @@
namespace Ryujinx.Graphics.Shader.Decoders
{
enum VideoType
{
U8 = 0,
U16 = 1,
U32 = 2,
Signed = 1 << 2,
S8 = Signed | U8,
S16 = Signed | U16,
S32 = Signed | U32
}
}