Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390)

* Update AOpCodeTable.cs

* Update AInstEmitSimdCvt.cs

* Update Pseudocode.cs

* Update Instructions.cs

* Update CpuTestSimd.cs

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update Instructions.cs

* Update CpuTestSimdReg.cs

* Update CpuTestSimd.cs

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update Instructions.cs

* Update CpuTestSimdReg.cs

* Add QCFlagBit.

* Add QCFlagBit.

ChocolArm64/AOpCodeTable.cs

@@ -255,6 +255,10 @@ namespace ChocolArm64
             SetA64("x00111100x110000000000xxxxxxxxxx", AInstEmit.Fcvtms_Gp,     typeof(AOpCodeSimdCvt));
             SetA64("x00111100x110001000000xxxxxxxxxx", AInstEmit.Fcvtmu_Gp,     typeof(AOpCodeSimdCvt));
             SetA64("0x0011100x100001011010xxxxxxxxxx", AInstEmit.Fcvtn_V,       typeof(AOpCodeSimd));
+            SetA64("010111100x100001101010xxxxxxxxxx", AInstEmit.Fcvtns_S,      typeof(AOpCodeSimd));
+            SetA64("0>0011100<100001101010xxxxxxxxxx", AInstEmit.Fcvtns_V,      typeof(AOpCodeSimd));
+            SetA64("011111100x100001101010xxxxxxxxxx", AInstEmit.Fcvtnu_S,      typeof(AOpCodeSimd));
+            SetA64("0>1011100<100001101010xxxxxxxxxx", AInstEmit.Fcvtnu_V,      typeof(AOpCodeSimd));
             SetA64("x00111100x101000000000xxxxxxxxxx", AInstEmit.Fcvtps_Gp,     typeof(AOpCodeSimdCvt));
             SetA64("x00111100x101001000000xxxxxxxxxx", AInstEmit.Fcvtpu_Gp,     typeof(AOpCodeSimdCvt));
             SetA64("x00111100x111000000000xxxxxxxxxx", AInstEmit.Fcvtzs_Gp,     typeof(AOpCodeSimdCvt));
@@ -365,6 +369,7 @@ namespace ChocolArm64
             SetA64("0x001110<<1xxxxx011101xxxxxxxxxx", AInstEmit.Sabd_V,        typeof(AOpCodeSimdReg));
             SetA64("0x001110<<1xxxxx011100xxxxxxxxxx", AInstEmit.Sabdl_V,       typeof(AOpCodeSimdReg));
             SetA64("0x001110<<100000011010xxxxxxxxxx", AInstEmit.Sadalp_V,      typeof(AOpCodeSimd));
+            SetA64("0x001110<<1xxxxx000000xxxxxxxxxx", AInstEmit.Saddl_V,       typeof(AOpCodeSimdReg));
             SetA64("0x001110<<100000001010xxxxxxxxxx", AInstEmit.Saddlp_V,      typeof(AOpCodeSimd));
             SetA64("0x001110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Saddw_V,       typeof(AOpCodeSimdReg));
             SetA64("x0011110xx100010000000xxxxxxxxxx", AInstEmit.Scvtf_Gp,      typeof(AOpCodeSimdCvt));
@@ -419,6 +424,7 @@ namespace ChocolArm64
             SetA64("0100111101xxxxxx000001xxxxxxxxxx", AInstEmit.Sshr_V,        typeof(AOpCodeSimdShImm));
             SetA64("0x00111100>>>xxx000101xxxxxxxxxx", AInstEmit.Ssra_V,        typeof(AOpCodeSimdShImm));
             SetA64("0100111101xxxxxx000101xxxxxxxxxx", AInstEmit.Ssra_V,        typeof(AOpCodeSimdShImm));
+            SetA64("0x001110<<1xxxxx001000xxxxxxxxxx", AInstEmit.Ssubl_V,       typeof(AOpCodeSimdReg));
             SetA64("0x001110<<1xxxxx001100xxxxxxxxxx", AInstEmit.Ssubw_V,       typeof(AOpCodeSimdReg));
             SetA64("0x00110000000000xxxxxxxxxxxxxxxx", AInstEmit.St__Vms,       typeof(AOpCodeSimdMemMs));
             SetA64("0x001100100xxxxxxxxxxxxxxxxxxxxx", AInstEmit.St__Vms,       typeof(AOpCodeSimdMemMs));
@@ -457,6 +463,8 @@ namespace ChocolArm64
             SetA64("0x101110<<1xxxxx101001xxxxxxxxxx", AInstEmit.Umaxp_V,       typeof(AOpCodeSimdReg));
             SetA64("0x101110<<1xxxxx011011xxxxxxxxxx", AInstEmit.Umin_V,        typeof(AOpCodeSimdReg));
             SetA64("0x101110<<1xxxxx101011xxxxxxxxxx", AInstEmit.Uminp_V,       typeof(AOpCodeSimdReg));
+            SetA64("0x101110<<1xxxxx100000xxxxxxxxxx", AInstEmit.Umlal_V,       typeof(AOpCodeSimdReg));
+            SetA64("0x101110<<1xxxxx101000xxxxxxxxxx", AInstEmit.Umlsl_V,       typeof(AOpCodeSimdReg));
             SetA64("0x001110000xxxxx001111xxxxxxxxxx", AInstEmit.Umov_S,        typeof(AOpCodeSimdIns));
             SetA64("0x101110<<1xxxxx110000xxxxxxxxxx", AInstEmit.Umull_V,       typeof(AOpCodeSimdReg));
             SetA64("01111110xx1xxxxx000011xxxxxxxxxx", AInstEmit.Uqadd_S,       typeof(AOpCodeSimdReg));
@@ -475,6 +483,7 @@ namespace ChocolArm64
             SetA64("0>101110<<100000001110xxxxxxxxxx", AInstEmit.Usqadd_V,      typeof(AOpCodeSimd));
             SetA64("0x10111100>>>xxx000101xxxxxxxxxx", AInstEmit.Usra_V,        typeof(AOpCodeSimdShImm));
             SetA64("0110111101xxxxxx000101xxxxxxxxxx", AInstEmit.Usra_V,        typeof(AOpCodeSimdShImm));
+            SetA64("0x101110<<1xxxxx001000xxxxxxxxxx", AInstEmit.Usubl_V,       typeof(AOpCodeSimdReg));
             SetA64("0x101110<<1xxxxx001100xxxxxxxxxx", AInstEmit.Usubw_V,       typeof(AOpCodeSimdReg));
             SetA64("0>001110<<0xxxxx000110xxxxxxxxxx", AInstEmit.Uzp1_V,        typeof(AOpCodeSimdReg));
             SetA64("0>001110<<0xxxxx010110xxxxxxxxxx", AInstEmit.Uzp2_V,        typeof(AOpCodeSimdReg));

ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs

@@ -1032,6 +1032,11 @@ namespace ChocolArm64.Instruction
             EmitAddLongPairwise(Context, Signed: true, Accumulate: true);
         }
 
+        public static void Saddl_V(AILEmitterCtx Context)
+        {
+            EmitVectorWidenRnRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Add));
+        }
+
         public static void Saddlp_V(AILEmitterCtx Context)
         {
             EmitAddLongPairwise(Context, Signed: true, Accumulate: false);
@@ -1217,6 +1222,11 @@ namespace ChocolArm64.Instruction
             });
         }
 
+        public static void Ssubl_V(AILEmitterCtx Context)
+        {
+            EmitVectorWidenRnRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Sub));
+        }
+
         public static void Ssubw_V(AILEmitterCtx Context)
         {
             EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Sub));
@@ -1391,6 +1401,24 @@ namespace ChocolArm64.Instruction
             EmitVectorPairwiseOpZx(Context, () => Context.EmitCall(MthdInfo));
         }
 
+        public static void Umlal_V(AILEmitterCtx Context)
+        {
+            EmitVectorWidenRnRmTernaryOpZx(Context, () =>
+            {
+                Context.Emit(OpCodes.Mul);
+                Context.Emit(OpCodes.Add);
+            });
+        }
+
+        public static void Umlsl_V(AILEmitterCtx Context)
+        {
+            EmitVectorWidenRnRmTernaryOpZx(Context, () =>
+            {
+                Context.Emit(OpCodes.Mul);
+                Context.Emit(OpCodes.Sub);
+            });
+        }
+
         public static void Umull_V(AILEmitterCtx Context)
         {
             EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul));
@@ -1450,6 +1478,11 @@ namespace ChocolArm64.Instruction
             EmitVectorSaturatingBinaryOpZx(Context, SaturatingFlags.Accumulate);
         }
 
+        public static void Usubl_V(AILEmitterCtx Context)
+        {
+            EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub));
+        }
+
         public static void Usubw_V(AILEmitterCtx Context)
         {
             EmitVectorWidenRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub));

ChocolArm64/Instruction/AInstEmitSimdCvt.cs

@@ -106,6 +106,26 @@ namespace ChocolArm64.Instruction
             }
         }
 
+        public static void Fcvtns_S(AILEmitterCtx Context)
+        {
+            EmitFcvtn(Context, Signed: true, Scalar: true);
+        }
+
+        public static void Fcvtns_V(AILEmitterCtx Context)
+        {
+            EmitFcvtn(Context, Signed: true, Scalar: false);
+        }
+
+        public static void Fcvtnu_S(AILEmitterCtx Context)
+        {
+            EmitFcvtn(Context, Signed: false, Scalar: true);
+        }
+
+        public static void Fcvtnu_V(AILEmitterCtx Context)
+        {
+            EmitFcvtn(Context, Signed: false, Scalar: false);
+        }
+
         public static void Fcvtps_Gp(AILEmitterCtx Context)
         {
             EmitFcvt_s_Gp(Context, () => EmitUnaryMathCall(Context, nameof(Math.Ceiling)));
@@ -250,6 +270,54 @@ namespace ChocolArm64.Instruction
             }
         }
 
+        private static void EmitFcvtn(AILEmitterCtx Context, bool Signed, bool Scalar)
+        {
+            AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
+
+            int SizeF = Op.Size & 1;
+            int SizeI = SizeF + 2;
+
+            int Bytes = Op.GetBitsCount() >> 3;
+            int Elems = !Scalar ? Bytes >> SizeI : 1;
+
+            if (Scalar && (SizeF == 0))
+            {
+                EmitVectorZeroLowerTmp(Context);
+            }
+
+            for (int Index = 0; Index < Elems; Index++)
+            {
+                EmitVectorExtractF(Context, Op.Rn, Index, SizeF);
+
+                EmitRoundMathCall(Context, MidpointRounding.ToEven);
+
+                if (SizeF == 0)
+                {
+                    AVectorHelper.EmitCall(Context, Signed
+                        ? nameof(AVectorHelper.SatF32ToS32)
+                        : nameof(AVectorHelper.SatF32ToU32));
+
+                    Context.Emit(OpCodes.Conv_U8);
+                }
+                else /* if (SizeF == 1) */
+                {
+                    AVectorHelper.EmitCall(Context, Signed
+                        ? nameof(AVectorHelper.SatF64ToS64)
+                        : nameof(AVectorHelper.SatF64ToU64));
+                }
+
+                EmitVectorInsertTmp(Context, Index, SizeI);
+            }
+
+            Context.EmitLdvectmp();
+            Context.EmitStvec(Op.Rd);
+
+            if ((Op.RegisterSize == ARegisterSize.SIMD64) || Scalar)
+            {
+                EmitVectorZeroUpper(Context, Op.Rd);
+            }
+        }
+
         private static void EmitFcvt_s_Gp(AILEmitterCtx Context, Action Emit)
         {
             EmitFcvt___Gp(Context, Emit, true);
@@ -569,4 +637,4 @@ namespace ChocolArm64.Instruction
             }
         }
     }
-}
+}

Ryujinx.Tests/Cpu/Tester/Instructions.cs

@@ -2685,6 +2685,154 @@ namespace Ryujinx.Tests.Cpu.Tester
             V(d, result);
         }
 
+        // fcvtns_advsimd.html#FCVTNS_asisdmisc_R
+        public static void Fcvtns_S(Bits sz, Bits Rn, Bits Rd)
+        {
+            const bool U = false;
+            const bool o2 = false;
+            const bool o1 = false;
+
+            /* Decode Scalar */
+            int d = (int)UInt(Rd);
+            int n = (int)UInt(Rn);
+
+            int esize = 32 << (int)UInt(sz);
+            int datasize = esize;
+            int elements = 1;
+
+            FPRounding rounding = FPDecodeRounding(Bits.Concat(o1, o2));
+
+            bool unsigned = (U == true);
+
+            /* Operation */
+            /* CheckFPAdvSIMDEnabled64(); */
+
+            Bits result = new Bits(datasize);
+            Bits operand = V(datasize, n);
+            Bits element;
+
+            for (int e = 0; e <= elements - 1; e++)
+            {
+                element = Elem(operand, e, esize);
+
+                Elem(result, e, esize, FPToFixed(esize, element, 0, unsigned, FPCR, rounding));
+            }
+
+            V(d, result);
+        }
+
+        // fcvtns_advsimd.html#FCVTNS_asimdmisc_R
+        public static void Fcvtns_V(bool Q, Bits sz, Bits Rn, Bits Rd)
+        {
+            const bool U = false;
+            const bool o2 = false;
+            const bool o1 = false;
+
+            /* Decode Vector */
+            int d = (int)UInt(Rd);
+            int n = (int)UInt(Rn);
+
+            /* if sz:Q == '10' then ReservedValue(); */
+
+            int esize = 32 << (int)UInt(sz);
+            int datasize = (Q ? 128 : 64);
+            int elements = datasize / esize;
+
+            FPRounding rounding = FPDecodeRounding(Bits.Concat(o1, o2));
+
+            bool unsigned = (U == true);
+
+            /* Operation */
+            /* CheckFPAdvSIMDEnabled64(); */
+
+            Bits result = new Bits(datasize);
+            Bits operand = V(datasize, n);
+            Bits element;
+
+            for (int e = 0; e <= elements - 1; e++)
+            {
+                element = Elem(operand, e, esize);
+
+                Elem(result, e, esize, FPToFixed(esize, element, 0, unsigned, FPCR, rounding));
+            }
+
+            V(d, result);
+        }
+
+        // fcvtnu_advsimd.html#FCVTNU_asisdmisc_R
+        public static void Fcvtnu_S(Bits sz, Bits Rn, Bits Rd)
+        {
+            const bool U = true;
+            const bool o2 = false;
+            const bool o1 = false;
+
+            /* Decode Scalar */
+            int d = (int)UInt(Rd);
+            int n = (int)UInt(Rn);
+
+            int esize = 32 << (int)UInt(sz);
+            int datasize = esize;
+            int elements = 1;
+
+            FPRounding rounding = FPDecodeRounding(Bits.Concat(o1, o2));
+
+            bool unsigned = (U == true);
+
+            /* Operation */
+            /* CheckFPAdvSIMDEnabled64(); */
+
+            Bits result = new Bits(datasize);
+            Bits operand = V(datasize, n);
+            Bits element;
+
+            for (int e = 0; e <= elements - 1; e++)
+            {
+                element = Elem(operand, e, esize);
+
+                Elem(result, e, esize, FPToFixed(esize, element, 0, unsigned, FPCR, rounding));
+            }
+
+            V(d, result);
+        }
+
+        // fcvtnu_advsimd.html#FCVTNU_asimdmisc_R
+        public static void Fcvtnu_V(bool Q, Bits sz, Bits Rn, Bits Rd)
+        {
+            const bool U = true;
+            const bool o2 = false;
+            const bool o1 = false;
+
+            /* Decode Vector */
+            int d = (int)UInt(Rd);
+            int n = (int)UInt(Rn);
+
+            /* if sz:Q == '10' then ReservedValue(); */
+
+            int esize = 32 << (int)UInt(sz);
+            int datasize = (Q ? 128 : 64);
+            int elements = datasize / esize;
+
+            FPRounding rounding = FPDecodeRounding(Bits.Concat(o1, o2));
+
+            bool unsigned = (U == true);
+
+            /* Operation */
+            /* CheckFPAdvSIMDEnabled64(); */
+
+            Bits result = new Bits(datasize);
+            Bits operand = V(datasize, n);
+            Bits element;
+
+            for (int e = 0; e <= elements - 1; e++)
+            {
+                element = Elem(operand, e, esize);
+
+                Elem(result, e, esize, FPToFixed(esize, element, 0, unsigned, FPCR, rounding));
+            }
+
+            V(d, result);
+        }
+
         // neg_advsimd.html#NEG_asisdmisc_R
         public static void Neg_S(Bits size, Bits Rn, Bits Rd)
         {
@@ -5122,6 +5270,57 @@ namespace Ryujinx.Tests.Cpu.Tester
             V(d, result);
         }
 
+        // saddl_advsimd.html
+        public static void Saddl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
+        {
+            const bool U = false;
+            const bool o1 = false;
+
+            /* Decode */
+            int d = (int)UInt(Rd);
+            int n = (int)UInt(Rn);
+            int m = (int)UInt(Rm);
+
+            /* if size == '11' then ReservedValue(); */
+
+            int esize = 8 << (int)UInt(size);
+            int datasize = 64;
+            int part = (int)UInt(Q);
+            int elements = datasize / esize;
+
+            bool sub_op = (o1 == true);
+            bool unsigned = (U == true);
+
+            /* Operation */
+            /* CheckFPAdvSIMDEnabled64(); */
+
+            Bits result = new Bits(2 * datasize);
+            Bits operand1 = Vpart(datasize, n, part);
+            Bits operand2 = Vpart(datasize, m, part);
+            BigInteger element1;
+            BigInteger element2;
+            BigInteger sum;
+
+            for (int e = 0; e <= elements - 1; e++)
+            {
+                element1 = Int(Elem(operand1, e, esize), unsigned);
+                element2 = Int(Elem(operand2, e, esize), unsigned);
+
+                if (sub_op)
+                {
+                    sum = element1 - element2;
+                }
+                else
+                {
+                    sum = element1 + element2;
+                }
+
+                Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0));
+            }
+
+            V(d, result);
+        }
+
         // saddw_advsimd.html
         public static void Saddw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
         {
@@ -5333,6 +5532,116 @@ namespace Ryujinx.Tests.Cpu.Tester
             V(d, result);
         }
 
+        // smlal_advsimd_vec.html
+        public static void Smlal_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
+        {
+            const bool U = false;
+            const bool o1 = false;
+
+            /* Decode */
+            int d = (int)UInt(Rd);
+            int n = (int)UInt(Rn);
+            int m = (int)UInt(Rm);
+
+            /* if size == '11' then ReservedValue(); */
+
+            int esize = 8 << (int)UInt(size);
+            int datasize = 64;
+            int part = (int)UInt(Q);
+            int elements = datasize / esize;
+
+            bool sub_op = (o1 == true);
+            bool unsigned = (U == true);
+
+            /* Operation */
+            /* CheckFPAdvSIMDEnabled64(); */
+
+            Bits result = new Bits(2 * datasize);
+            Bits operand1 = Vpart(datasize, n, part);
+            Bits operand2 = Vpart(datasize, m, part);
+            Bits operand3 = V(2 * datasize, d);
+            BigInteger element1;
+            BigInteger element2;
+            Bits product;
+            Bits accum;
+
+            for (int e = 0; e <= elements - 1; e++)
+            {
+                element1 = Int(Elem(operand1, e, esize), unsigned);
+                element2 = Int(Elem(operand2, e, esize), unsigned);
+
+                product = (element1 * element2).SubBigInteger(2 * esize - 1, 0);
+
+                if (sub_op)
+                {
+                    accum = Elem(operand3, e, 2 * esize) - product;
+                }
+                else
+                {
+                    accum = Elem(operand3, e, 2 * esize) + product;
+                }
+
+                Elem(result, e, 2 * esize, accum);
+            }
+
+            V(d, result);
+        }
+
+        // smlsl_advsimd_vec.html
+        public static void Smlsl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
+        {
+            const bool U = false;
+            const bool o1 = true;
+
+            /* Decode */
+            int d = (int)UInt(Rd);
+            int n = (int)UInt(Rn);
+            int m = (int)UInt(Rm);
+
+            /* if size == '11' then ReservedValue(); */
+
+            int esize = 8 << (int)UInt(size);
+            int datasize = 64;
+            int part = (int)UInt(Q);
+            int elements = datasize / esize;
+
+            bool sub_op = (o1 == true);
+            bool unsigned = (U == true);
+
+            /* Operation */
+            /* CheckFPAdvSIMDEnabled64(); */
+
+            Bits result = new Bits(2 * datasize);
+            Bits operand1 = Vpart(datasize, n, part);
+            Bits operand2 = Vpart(datasize, m, part);
+            Bits operand3 = V(2 * datasize, d);
+            BigInteger element1;
+            BigInteger element2;
+            Bits product;
+            Bits accum;
+
+            for (int e = 0; e <= elements - 1; e++)
+            {
+                element1 = Int(Elem(operand1, e, esize), unsigned);
+                element2 = Int(Elem(operand2, e, esize), unsigned);
+
+                product = (element1 * element2).SubBigInteger(2 * esize - 1, 0);
+
+                if (sub_op)
+                {
+                    accum = Elem(operand3, e, 2 * esize) - product;
+                }
+                else
+                {
+                    accum = Elem(operand3, e, 2 * esize) + product;
+                }
+
+                Elem(result, e, 2 * esize, accum);
+            }
+
+            V(d, result);
+        }
+
         // sqadd_advsimd.html#SQADD_asisdsame_only
         public static void Sqadd_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
         {
@@ -5771,6 +6080,57 @@ namespace Ryujinx.Tests.Cpu.Tester
             V(d, result);
         }
 
+        // ssubl_advsimd.html
+        public static void Ssubl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
+        {
+            const bool U = false;
+            const bool o1 = true;
+
+            /* Decode */
+            int d = (int)UInt(Rd);
+            int n = (int)UInt(Rn);
+            int m = (int)UInt(Rm);
+
+            /* if size == '11' then ReservedValue(); */
+
+            int esize = 8 << (int)UInt(size);
+            int datasize = 64;
+            int part = (int)UInt(Q);
+            int elements = datasize / esize;
+
+            bool sub_op = (o1 == true);
+            bool unsigned = (U == true);
+
+            /* Operation */
+            /* CheckFPAdvSIMDEnabled64(); */
+
+            Bits result = new Bits(2 * datasize);
+            Bits operand1 = Vpart(datasize, n, part);
+            Bits operand2 = Vpart(datasize, m, part);
+            BigInteger element1;
+            BigInteger element2;
+            BigInteger sum;
+
+            for (int e = 0; e <= elements - 1; e++)
+            {
+                element1 = Int(Elem(operand1, e, esize), unsigned);
+                element2 = Int(Elem(operand2, e, esize), unsigned);
+
+                if (sub_op)
+                {
+                    sum = element1 - element2;
+                }
+                else
+                {
+                    sum = element1 + element2;
+                }
+
+                Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0));
+            }
+
+            V(d, result);
+        }
+
         // ssubw_advsimd.html
         public static void Ssubw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
         {
@@ -6212,6 +6572,57 @@ namespace Ryujinx.Tests.Cpu.Tester
             V(d, result);
         }
 
+        // uaddl_advsimd.html
+        public static void Uaddl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
+        {
+            const bool U = true;
+            const bool o1 = false;
+
+            /* Decode */
+            int d = (int)UInt(Rd);
+            int n = (int)UInt(Rn);
+            int m = (int)UInt(Rm);
+
+            /* if size == '11' then ReservedValue(); */
+
+            int esize = 8 << (int)UInt(size);
+            int datasize = 64;
+            int part = (int)UInt(Q);
+            int elements = datasize / esize;
+
+            bool sub_op = (o1 == true);
+            bool unsigned = (U == true);
+
+            /* Operation */
+            /* CheckFPAdvSIMDEnabled64(); */
+
+            Bits result = new Bits(2 * datasize);
+            Bits operand1 = Vpart(datasize, n, part);
+            Bits operand2 = Vpart(datasize, m, part);
+            BigInteger element1;
+            BigInteger element2;
+            BigInteger sum;
+
+            for (int e = 0; e <= elements - 1; e++)
+            {
+                element1 = Int(Elem(operand1, e, esize), unsigned);
+                element2 = Int(Elem(operand2, e, esize), unsigned);
+
+                if (sub_op)
+                {
+                    sum = element1 - element2;
+                }
+                else
+                {
+                    sum = element1 + element2;
+                }
+
+                Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0));
+            }
+
+            V(d, result);
+        }
+
         // uaddw_advsimd.html
         public static void Uaddw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
         {
@@ -6345,6 +6756,116 @@ namespace Ryujinx.Tests.Cpu.Tester
             V(d, result);
         }
 
+        // umlal_advsimd_vec.html
+        public static void Umlal_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
+        {
+            const bool U = true;
+            const bool o1 = false;
+
+            /* Decode */
+            int d = (int)UInt(Rd);
+            int n = (int)UInt(Rn);
+            int m = (int)UInt(Rm);
+
+            /* if size == '11' then ReservedValue(); */
+
+            int esize = 8 << (int)UInt(size);
+            int datasize = 64;
+            int part = (int)UInt(Q);
+            int elements = datasize / esize;
+
+            bool sub_op = (o1 == true);
+            bool unsigned = (U == true);
+
+            /* Operation */
+            /* CheckFPAdvSIMDEnabled64(); */
+
+            Bits result = new Bits(2 * datasize);
+            Bits operand1 = Vpart(datasize, n, part);
+            Bits operand2 = Vpart(datasize, m, part);
+            Bits operand3 = V(2 * datasize, d);
+            BigInteger element1;
+            BigInteger element2;
+            Bits product;
+            Bits accum;
+
+            for (int e = 0; e <= elements - 1; e++)
+            {
+                element1 = Int(Elem(operand1, e, esize), unsigned);
+                element2 = Int(Elem(operand2, e, esize), unsigned);
+
+                product = (element1 * element2).SubBigInteger(2 * esize - 1, 0);
+
+                if (sub_op)
+                {
+                    accum = Elem(operand3, e, 2 * esize) - product;
+                }
+                else
+                {
+                    accum = Elem(operand3, e, 2 * esize) + product;
+                }
+
+                Elem(result, e, 2 * esize, accum);
+            }
+
+            V(d, result);
+        }
+
+        // umlsl_advsimd_vec.html
+        public static void Umlsl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
+        {
+            const bool U = true;
+            const bool o1 = true;
+
+            /* Decode */
+            int d = (int)UInt(Rd);
+            int n = (int)UInt(Rn);
+            int m = (int)UInt(Rm);
+
+            /* if size == '11' then ReservedValue(); */
+
+            int esize = 8 << (int)UInt(size);
+            int datasize = 64;
+            int part = (int)UInt(Q);
+            int elements = datasize / esize;
+
+            bool sub_op = (o1 == true);
+            bool unsigned = (U == true);
+
+            /* Operation */
+            /* CheckFPAdvSIMDEnabled64(); */
+
+            Bits result = new Bits(2 * datasize);
+            Bits operand1 = Vpart(datasize, n, part);
+            Bits operand2 = Vpart(datasize, m, part);
+            Bits operand3 = V(2 * datasize, d);
+            BigInteger element1;
+            BigInteger element2;
+            Bits product;
+            Bits accum;
+
+            for (int e = 0; e <= elements - 1; e++)
+            {
+                element1 = Int(Elem(operand1, e, esize), unsigned);
+                element2 = Int(Elem(operand2, e, esize), unsigned);
+
+                product = (element1 * element2).SubBigInteger(2 * esize - 1, 0);
+
+                if (sub_op)
+                {
+                    accum = Elem(operand3, e, 2 * esize) - product;
+                }
+                else
+                {
+                    accum = Elem(operand3, e, 2 * esize) + product;
+                }
+
+                Elem(result, e, 2 * esize, accum);
+            }
+
+            V(d, result);
+        }
+
         // uqadd_advsimd.html#UQADD_asisdsame_only
         public static void Uqadd_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
         {
@@ -6579,6 +7100,57 @@ namespace Ryujinx.Tests.Cpu.Tester
             V(d, result);
         }
 
+        // usubl_advsimd.html
+        public static void Usubl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
+        {
+            const bool U = true;
+            const bool o1 = true;
+
+            /* Decode */
+            int d = (int)UInt(Rd);
+            int n = (int)UInt(Rn);
+            int m = (int)UInt(Rm);
+
+            /* if size == '11' then ReservedValue(); */
+
+            int esize = 8 << (int)UInt(size);
+            int datasize = 64;
+            int part = (int)UInt(Q);
+            int elements = datasize / esize;
+
+            bool sub_op = (o1 == true);
+            bool unsigned = (U == true);
+
+            /* Operation */
+            /* CheckFPAdvSIMDEnabled64(); */
+
+            Bits result = new Bits(2 * datasize);
+            Bits operand1 = Vpart(datasize, n, part);
+            Bits operand2 = Vpart(datasize, m, part);
+            BigInteger element1;
+            BigInteger element2;
+            BigInteger sum;
+
+            for (int e = 0; e <= elements - 1; e++)
+            {
+                element1 = Int(Elem(operand1, e, esize), unsigned);
+                element2 = Int(Elem(operand2, e, esize), unsigned);
+
+                if (sub_op)
+                {
+                    sum = element1 - element2;
+                }
+                else
+                {
+                    sum = element1 + element2;
+                }
+
+                Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0));
+            }
+
+            V(d, result);
+        }
+
         // usubw_advsimd.html
         public static void Usubw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
         {

Ryujinx.Tests/Cpu/Tester/Pseudocode.cs

@@ -5,21 +5,19 @@
 
 // https://alastairreid.github.io/asl-lexical-syntax/
 
-// | ------------------------|----------------------------------- |
+// | ------------------------|-------------------------------- |
-// | ASL                     | C#                                 |
+// | ASL                     | C#                              |
-// | ------------------------|----------------------------------- |
+// | ------------------------|-------------------------------- |
-// | bit, bits(1); boolean   | bool                               |
+// | bit, bits(1); boolean   | bool                            |
-// | bits                    | Bits                               |
+// | bits                    | Bits                            |
-// | integer                 | BigInteger, int                    |
+// | integer                 | BigInteger, int                 |
-// | real                    | decimal                            |
+// | real                    | decimal; double, float          |
-// | ------------------------|----------------------------------- |
+// | ------------------------|-------------------------------- |
-// | '0'; FALSE              | false                              |
+// | '0'; FALSE              | false                           |
-// | '1'; TRUE               | true                               |
+// | '1'; TRUE               | true                            |
-// | '010'                   | "010"                              |
+// | '010'                   | "010"                           |
-// | bitsX IN {bitsY, bitsZ} | (bitsX == bitsY || bitsX == bitsZ) |
+// | DIV, MOD                | /, %                            |
-// | DIV                     | /                                  |
+// | ------------------------|-------------------------------- |
-// | MOD                     | %                                  |
-// | ------------------------|----------------------------------- |
 
 using System;
 using System.Numerics;
@@ -107,6 +105,7 @@ namespace Ryujinx.Tests.Cpu.Tester
             /* SP_EL1 = bits(64) UNKNOWN; */
             SP_EL1.SetAll(false);
 
+            FPCR.SetAll(false); // TODO: Add named fields.
             FPSR.SetAll(false); // TODO: Add named fields.
         }
 
@@ -458,6 +457,7 @@ namespace Ryujinx.Tests.Cpu.Tester
 #endregion
 
 #region "instrs/vector/reduce/reduceop/"
+        // shared_pseudocode.html#impl-aarch64.Reduce.3
         public static Bits Reduce(ReduceOp op, Bits input, int esize)
         {
             int N = input.Count;
@@ -528,6 +528,7 @@ namespace Ryujinx.Tests.Cpu.Tester
             SP_EL0 = new Bits(64, false);
             SP_EL1 = new Bits(64, false);
 
+            FPCR = new Bits(32, false); // TODO: Add named fields.
             FPSR = new Bits(32, false); // TODO: Add named fields.
 
             PSTATE.N = false;
@@ -817,6 +818,36 @@ namespace Ryujinx.Tests.Cpu.Tester
             return (decimal)value;
         }
 
+        /* */
+        public static float Real_32(BigInteger value)
+        {
+            if (value == BigInteger.Pow((BigInteger)2.0f, 1000))
+            {
+                return float.PositiveInfinity;
+            }
+            if (value == -BigInteger.Pow((BigInteger)2.0f, 1000))
+            {
+                return float.NegativeInfinity;
+            }
+
+            return (float)value;
+        }
+
+        /* */
+        public static double Real_64(BigInteger value)
+        {
+            if (value == BigInteger.Pow((BigInteger)2.0, 10000))
+            {
+                return double.PositiveInfinity;
+            }
+            if (value == -BigInteger.Pow((BigInteger)2.0, 10000))
+            {
+                return double.NegativeInfinity;
+            }
+
+            return (double)value;
+        }
+
         // shared_pseudocode.html#impl-shared.ROR.2
         public static Bits ROR(Bits x, int shift)
         {
@@ -881,6 +912,36 @@ namespace Ryujinx.Tests.Cpu.Tester
             return (BigInteger)Decimal.Floor(x);
         }
 
+        /* */
+        public static BigInteger RoundDown_32(float x)
+        {
+            if (float.IsPositiveInfinity(x))
+            {
+                return BigInteger.Pow((BigInteger)2.0f, 1000);
+            }
+            if (float.IsNegativeInfinity(x))
+            {
+                return -BigInteger.Pow((BigInteger)2.0f, 1000);
+            }
+
+            return (BigInteger)MathF.Floor(x);
+        }
+
+        /* */
+        public static BigInteger RoundDown_64(double x)
+        {
+            if (double.IsPositiveInfinity(x))
+            {
+                return BigInteger.Pow((BigInteger)2.0, 10000);
+            }
+            if (double.IsNegativeInfinity(x))
+            {
+                return -BigInteger.Pow((BigInteger)2.0, 10000);
+            }
+
+            return (BigInteger)Math.Floor(x);
+        }
+
         // shared_pseudocode.html#impl-shared.RoundTowardsZero.1
         public static BigInteger RoundTowardsZero(decimal x)
         {
@@ -1091,6 +1152,398 @@ namespace Ryujinx.Tests.Cpu.Tester
         }
 #endregion
 
+#region "functions/float/fpdecoderounding/"
+        /* shared_pseudocode.html#impl-shared.FPDecodeRounding.1 */
+        public static FPRounding FPDecodeRounding(Bits rmode)
+        {
+            switch (rmode)
+            {
+                default:
+                case Bits bits when bits == "00":
+                    return FPRounding.FPRounding_TIEEVEN; // N
+                case Bits bits when bits == "01":
+                    return FPRounding.FPRounding_POSINF;  // P
+                case Bits bits when bits == "10":
+                    return FPRounding.FPRounding_NEGINF;  // M
+                case Bits bits when bits == "11":
+                    return FPRounding.FPRounding_ZERO;    // Z
+            }
+        }
+#endregion
+
+#region "functions/float/fpexc/"
+        // shared_pseudocode.html#FPExc
+        public enum FPExc {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow,
+                           FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm};
+#endregion
+
+#region "functions/float/fpprocessexception/"
+        // shared_pseudocode.html#impl-shared.FPProcessException.2
+        public static void FPProcessException(FPExc exception, Bits _fpcr)
+        {
+            Bits fpcr = new Bits(_fpcr); // Clone.
+
+            int cumul;
+
+            // Determine the cumulative exception bit number
+            switch (exception)
+            {
+                default:
+                case FPExc.FPExc_InvalidOp:    cumul = 0; break;
+                case FPExc.FPExc_DivideByZero: cumul = 1; break;
+                case FPExc.FPExc_Overflow:     cumul = 2; break;
+                case FPExc.FPExc_Underflow:    cumul = 3; break;
+                case FPExc.FPExc_Inexact:      cumul = 4; break;
+                case FPExc.FPExc_InputDenorm:  cumul = 7; break;
+            }
+
+            int enable = cumul + 8;
+
+            if (fpcr[enable])
+            {
+                // Trapping of the exception enabled.
+                // It is IMPLEMENTATION DEFINED whether the enable bit may be set at all, and
+                // if so then how exceptions may be accumulated before calling FPTrapException()
+                /* IMPLEMENTATION_DEFINED "floating-point trap handling"; */
+
+                throw new NotImplementedException();
+            }/*
+            else if (UsingAArch32())
+            {
+                // Set the cumulative exception bit
+                FPSCR<cumul> = '1';
+            }*/
+            else
+            {
+                // Set the cumulative exception bit
+                FPSR[cumul] = true;
+            }
+        }
+#endregion
+
+#region "functions/float/fprounding/"
+        // shared_pseudocode.html#FPRounding
+        public enum FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF,
+                                FPRounding_NEGINF, FPRounding_ZERO,
+                                FPRounding_TIEAWAY, FPRounding_ODD};
+#endregion
+
+#region "functions/float/fptofixed/"
+        /* shared_pseudocode.html#impl-shared.FPToFixed.5 */
+        public static Bits FPToFixed(int M, Bits op, int fbits, bool unsigned, Bits _fpcr, FPRounding rounding)
+        {
+            int N = op.Count;
+
+            /* assert N IN {16,32,64}; */
+            /* assert M IN {16,32,64}; */
+            /* assert fbits >= 0; */
+            /* assert rounding != FPRounding_ODD; */
+
+            Bits fpcr = new Bits(_fpcr); // Clone.
+
+            if (N == 16)
+            {
+                throw new NotImplementedException();
+            }
+            else if (N == 32)
+            {
+                // Unpack using fpcr to determine if subnormals are flushed-to-zero
+                (FPType type, bool sign, float value) = FPUnpack_32(op, fpcr);
+
+                // If NaN, set cumulative flag or take exception
+                if (type == FPType.FPType_SNaN || type == FPType.FPType_QNaN)
+                {
+                    FPProcessException(FPExc.FPExc_InvalidOp, fpcr);
+                }
+
+                // Scale by fractional bits and produce integer rounded towards minus-infinity
+                value = value * MathF.Pow(2.0f, fbits);
+                BigInteger int_result = RoundDown_32(value);
+                float error = value - Real_32(int_result);
+
+                if (float.IsNaN(error))
+                {
+                    error = 0.0f;
+                }
+
+                // Determine whether supplied rounding mode requires an increment
+                bool round_up;
+
+                switch (rounding)
+                {
+                    default:
+                    case FPRounding.FPRounding_TIEEVEN:
+                        round_up = (error > 0.5f || (error == 0.5f && int_result.SubBigInteger(0)));
+                        break;
+                    case FPRounding.FPRounding_POSINF:
+                        round_up = (error != 0.0f);
+                        break;
+                    case FPRounding.FPRounding_NEGINF:
+                        round_up = false;
+                        break;
+                    case FPRounding.FPRounding_ZERO:
+                        round_up = (error != 0.0f && int_result < (BigInteger)0);
+                        break;
+                    case FPRounding.FPRounding_TIEAWAY:
+                        round_up = (error > 0.5f || (error == 0.5f && int_result >= (BigInteger)0));
+                        break;
+                }
+
+                if (round_up)
+                {
+                    int_result = int_result + 1;
+                }
+
+                // Generate saturated result and exceptions
+                (Bits result, bool overflow) = SatQ(int_result, M, unsigned);
+
+                if (overflow)
+                {
+                    FPProcessException(FPExc.FPExc_InvalidOp, fpcr);
+                }
+                else if (error != 0.0f)
+                {
+                    FPProcessException(FPExc.FPExc_Inexact, fpcr);
+                }
+
+                return result;
+            }
+            else /* if (N == 64) */
+            {
+                // Unpack using fpcr to determine if subnormals are flushed-to-zero
+                (FPType type, bool sign, double value) = FPUnpack_64(op, fpcr);
+
+                // If NaN, set cumulative flag or take exception
+                if (type == FPType.FPType_SNaN || type == FPType.FPType_QNaN)
+                {
+                    FPProcessException(FPExc.FPExc_InvalidOp, fpcr);
+                }
+
+                // Scale by fractional bits and produce integer rounded towards minus-infinity
+                value = value * Math.Pow(2.0, fbits);
+                BigInteger int_result = RoundDown_64(value);
+                double error = value - Real_64(int_result);
+
+                if (double.IsNaN(error))
+                {
+                    error = 0.0;
+                }
+
+                // Determine whether supplied rounding mode requires an increment
+                bool round_up;
+
+                switch (rounding)
+                {
+                    default:
+                    case FPRounding.FPRounding_TIEEVEN:
+                        round_up = (error > 0.5 || (error == 0.5 && int_result.SubBigInteger(0)));
+                        break;
+                    case FPRounding.FPRounding_POSINF:
+                        round_up = (error != 0.0);
+                        break;
+                    case FPRounding.FPRounding_NEGINF:
+                        round_up = false;
+                        break;
+                    case FPRounding.FPRounding_ZERO:
+                        round_up = (error != 0.0 && int_result < (BigInteger)0);
+                        break;
+                    case FPRounding.FPRounding_TIEAWAY:
+                        round_up = (error > 0.5 || (error == 0.5 && int_result >= (BigInteger)0));
+                        break;
+                }
+
+                if (round_up)
+                {
+                    int_result = int_result + 1;
+                }
+
+                // Generate saturated result and exceptions
+                (Bits result, bool overflow) = SatQ(int_result, M, unsigned);
+
+                if (overflow)
+                {
+                    FPProcessException(FPExc.FPExc_InvalidOp, fpcr);
+                }
+                else if (error != 0.0)
+                {
+                    FPProcessException(FPExc.FPExc_Inexact, fpcr);
+                }
+
+                return result;
+            }
+        }
+#endregion
+
+#region "functions/float/fptype/"
+        // shared_pseudocode.html#FPType
+        public enum FPType {FPType_Nonzero, FPType_Zero, FPType_Infinity,
+                            FPType_QNaN, FPType_SNaN};
+#endregion
+
+#region "functions/float/fpunpack/"
+        /* shared_pseudocode.html#impl-shared.FPUnpack.2 */
+        /* shared_pseudocode.html#impl-shared.FPUnpackBase.2 */
+        /*public static (FPType, bool, real) FPUnpack_16(Bits fpval, Bits _fpcr)
+        {
+            int N = fpval.Count;
+
+            // assert N == 16;
+
+            Bits fpcr = new Bits(_fpcr); // Clone.
+
+            fpcr[26] = false;
+
+            return FPUnpackBase_16(fpval, fpcr);
+        }*/
+        public static (FPType, bool, float) FPUnpack_32(Bits fpval, Bits _fpcr)
+        {
+            int N = fpval.Count;
+
+            /* assert N == 32; */
+
+            Bits fpcr = new Bits(_fpcr); // Clone.
+
+            FPType type;
+            float value;
+
+            bool sign   = fpval[31];
+            Bits exp32  = fpval[30, 23];
+            Bits frac32 = fpval[22, 0];
+
+            if (IsZero(exp32))
+            {
+                // Produce zero if value is zero or flush-to-zero is selected.
+                if (IsZero(frac32) || fpcr[24])
+                {
+                    type = FPType.FPType_Zero;
+                    value = 0.0f;
+
+                    // Denormalized input flushed to zero
+                    if (!IsZero(frac32))
+                    {
+                        FPProcessException(FPExc.FPExc_InputDenorm, fpcr);
+                    }
+                }
+                else
+                {
+                    type = FPType.FPType_Nonzero;
+                    value = MathF.Pow(2.0f, -126) * (Real_32(UInt(frac32)) * MathF.Pow(2.0f, -23));
+                }
+            }
+            else if (IsOnes(exp32))
+            {
+                if (IsZero(frac32))
+                {
+                    type = FPType.FPType_Infinity;
+                    /* value = 2.0^1000000; */
+                    value = MathF.Pow(2.0f, 1000);
+                }
+                else
+                {
+                    type = frac32[22] ? FPType.FPType_QNaN : FPType.FPType_SNaN;
+                    value = 0.0f;
+                }
+            }
+            else
+            {
+                type = FPType.FPType_Nonzero;
+                value = MathF.Pow(2.0f, (int)UInt(exp32) - 127) * (1.0f + Real_32(UInt(frac32)) * MathF.Pow(2.0f, -23));
+            }
+
+            if (sign)
+            {
+                value = -value;
+            }
+
+            return (type, sign, value);
+        }
+        public static (FPType, bool, double) FPUnpack_64(Bits fpval, Bits _fpcr)
+        {
+            int N = fpval.Count;
+
+            /* assert N == 64; */
+
+            Bits fpcr = new Bits(_fpcr); // Clone.
+
+            FPType type;
+            double value;
+
+            bool sign   = fpval[63];
+            Bits exp64  = fpval[62, 52];
+            Bits frac64 = fpval[51, 0];
+
+            if (IsZero(exp64))
+            {
+                // Produce zero if value is zero or flush-to-zero is selected.
+                if (IsZero(frac64) || fpcr[24])
+                {
+                    type = FPType.FPType_Zero;
+                    value = 0.0;
+
+                    // Denormalized input flushed to zero
+                    if (!IsZero(frac64))
+                    {
+                        FPProcessException(FPExc.FPExc_InputDenorm, fpcr);
+                    }
+                }
+                else
+                {
+                    type = FPType.FPType_Nonzero;
+                    value = Math.Pow(2.0, -1022) * (Real_64(UInt(frac64)) * Math.Pow(2.0, -52));
+                }
+            }
+            else if (IsOnes(exp64))
+            {
+                if (IsZero(frac64))
+                {
+                    type = FPType.FPType_Infinity;
+                    /* value = 2.0^1000000; */
+                    value = Math.Pow(2.0, 10000);
+                }
+                else
+                {
+                    type = frac64[51] ? FPType.FPType_QNaN : FPType.FPType_SNaN;
+                    value = 0.0;
+                }
+            }
+            else
+            {
+                type = FPType.FPType_Nonzero;
+                value = Math.Pow(2.0, (int)UInt(exp64) - 1023) * (1.0 + Real_64(UInt(frac64)) * Math.Pow(2.0, -52));
+            }
+
+            if (sign)
+            {
+                value = -value;
+            }
+
+            return (type, sign, value);
+        }
+
+        /* shared_pseudocode.html#impl-shared.FPUnpackCV.2 */
+        /* shared_pseudocode.html#impl-shared.FPUnpackBase.2 */
+        /*public static (FPType, bool, real) FPUnpackCV_16(Bits fpval, Bits _fpcr)
+        {
+            int N = fpval.Count;
+
+            // assert N == 16;
+
+            Bits fpcr = new Bits(_fpcr); // Clone.
+
+            fpcr[19] = false;
+
+            return FPUnpackBase_16(fpval, fpcr);
+        }*/
+        public static (FPType, bool, float) FPUnpackCV_32(Bits fpval, Bits _fpcr)
+        {
+            return FPUnpack_32(fpval, _fpcr);
+        }
+        public static (FPType, bool, double) FPUnpackCV_64(Bits fpval, Bits _fpcr)
+        {
+            return FPUnpack_64(fpval, _fpcr);
+        }
+#endregion
+
 #region "functions/integer/"
         /* shared_pseudocode.html#impl-shared.AddWithCarry.3 */
         public static (Bits, Bits) AddWithCarry(int N, Bits x, Bits y, bool carry_in)
@@ -1117,7 +1570,12 @@ namespace Ryujinx.Tests.Cpu.Tester
         public static Bits SP_EL0;
         public static Bits SP_EL1;
 
+        public static Bits FPCR; // TODO: Add named fields.
+        // [ 31 | 30 | 29 | 28 | 27 | 26  | 25 | 24 | 23 22 | 21 20  | 19   | 18 17 16 | 15  | 14 | 13 | 12  | 11  | 10  | 9   | 8   | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 ]
+        // [ 0  | 0  | 0  | 0  | 0  | AHP | DN | FZ | RMode | Stride | FZ16 | Len      | IDE | 0  | 0  | IXE | UFE | OFE | DZE | IOE | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 ]
         public static Bits FPSR; // TODO: Add named fields.
+        // [ 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7   | 6 | 5 | 4   | 3   | 2   | 1   | 0   ]
+        // [ N  | Z  | C  | V  | QC | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0  | 0 | 0 | IDC | 0 | 0 | IXC | UFC | OFC | DZC | IOC ]
 #endregion
 
 #region "functions/system/"
@@ -1178,6 +1636,8 @@ namespace Ryujinx.Tests.Cpu.Tester
         /* shared_pseudocode.html#impl-shared.HaveEL.1 */
         public static bool HaveEL(Bits el)
         {
+            // TODO: Implement ASL: "IN" as C#: "Bits.In()".
+            /* if el IN {EL1,EL0} then */
             if (el == EL1 || el == EL0)
             {
                 return true; // EL1 and EL0 must exist