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Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)
* Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions * Address PR feedback * Address PR feedback * Remove another useless temp var * nit: Alignment * Replace Context.CurrOp.GetBitsCount() with Op.GetBitsCount() * Fix encodings and move flag bit test out of the loop
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@@ -363,7 +363,7 @@ namespace ChocolArm64.Instruction
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = (!Scalar ? Bytes >> Op.Size : 1);
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ulong SzMask = ulong.MaxValue >> (64 - (8 << Op.Size));
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@@ -407,7 +407,7 @@ namespace ChocolArm64.Instruction
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = (!Scalar ? Bytes >> Op.Size : 1);
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ulong SzMask = ulong.MaxValue >> (64 - (8 << Op.Size));
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@@ -454,7 +454,7 @@ namespace ChocolArm64.Instruction
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int SizeF = Op.Size & 1;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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int Bytes = Op.GetBitsCount() >> 3;
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for (int Index = 0; Index < Bytes >> SizeF + 2; Index++)
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{
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