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T32: Implement ALU (shifted register) instructions (#3135)

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* T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register)

* OpCodeTable: Sort T32 list

* Tests: Rename RandomTestCase to PrecomputedThumbTestCase

* T32: Tests for AluRsImm instructions

* fix nit

* fix nit 2
This commit is contained in:
merry
2022-02-22 22:11:28 +00:00
committed by GitHub
parent 0a24aa6af2
commit 7b35ebc64a
11 changed files with 758 additions and 144 deletions
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17
ARMeilleure/Instructions/InstEmitAlu32.cs
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@ -244,6 +244,23 @@ namespace ARMeilleure.Instructions
EmitAluStore(context, res);
}
public static void Orn(ArmEmitterContext context)
{
IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
Operand n = GetAluN(context);
Operand m = GetAluM(context);
Operand res = context.BitwiseOr(n, context.BitwiseNot(m));
if (ShouldSetFlags(context))
{
EmitNZFlagsCheck(context, res);
}
EmitAluStore(context, res);
}
public static void Pkh(ArmEmitterContext context)
{
OpCode32AluRsImm op = (OpCode32AluRsImm)context.CurrOp;

2
ARMeilleure/Instructions/InstEmitHelper.cs
View File

@ -12,7 +12,7 @@ namespace ARMeilleure.Instructions
{
public static bool IsThumb(OpCode op)
{
return op is OpCodeT16;
return op is OpCodeT16 || op is OpCodeT32;
}
public static Operand GetExtendedM(ArmEmitterContext context, int rm, IntType type)