daniel/Ryujinx
1
0
Fork 0
mirror of https://github.com/Ryujinx/Ryujinx.git synced 2025-06-29 16:20:47 -07:00
Code Issues Packages Projects Releases Wiki Activity

Fix EXT/Widening instruction carrying garbage values on some cases, fix ABD (it shouldn't accumulate, this is another variation of the instruction)

Browse Source
This commit is contained in:
gdkchan
2018-03-30 17:37:31 -03:00
parent 76ac31add6
commit 916540ff41
3 changed files with 21 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
ChocolArm64/Instruction/AInstEmitSimdHelper.cs
View File

@ -447,6 +447,9 @@ namespace ChocolArm64.Instruction
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
Context.EmitLdvec(Op.Rd);
Context.EmitStvectmp();
int Elems = 8 >> Op.Size;
int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
@ -489,6 +492,9 @@ namespace ChocolArm64.Instruction
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
Context.EmitLdvec(Op.Rd);
Context.EmitStvectmp();
int Elems = 8 >> Op.Size;
int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;