mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2025-06-28 15:40:47 -07:00
Replace unicorn bindings with Nuget package (#4378)
* Replace unicorn bindings with Nuget package * Use nameof for ValueSource args * Remove redundant code from test projects * Fix wrong values for EmuStart() Add notes to address this later again * Improve formatting * Fix formatting/alignment issues
This commit is contained in:
TSRBerry
GitHub
@ -6,7 +6,6 @@ using Ryujinx.Cpu.Jit;
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using Ryujinx.Memory;
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using Ryujinx.Tests.Unicorn;
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using System;
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using MemoryPermission = Ryujinx.Tests.Unicorn.MemoryPermission;
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namespace Ryujinx.Tests.Cpu
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@ -33,18 +32,10 @@ namespace Ryujinx.Tests.Cpu
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private CpuContext _cpuContext;
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private static bool _unicornAvailable;
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private UnicornAArch64 _unicornEmu;
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private bool _usingMemory;
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[OneTimeSetUp]
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public void OneTimeSetup()
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{
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_unicornAvailable = UnicornAArch64.IsAvailable();
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Assume.That(_unicornAvailable, "Unicorn is not available");
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}
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[SetUp]
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public void Setup()
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{
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@ -65,23 +56,17 @@ namespace Ryujinx.Tests.Cpu
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Optimizations.AllowLcqInFunctionTable = false;
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Optimizations.UseUnmanagedDispatchLoop = false;
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if (_unicornAvailable)
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{
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_unicornEmu = new UnicornAArch64();
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_unicornEmu.MemoryMap(CodeBaseAddress, Size, MemoryPermission.READ | MemoryPermission.EXEC);
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_unicornEmu.MemoryMap(DataBaseAddress, Size, MemoryPermission.READ | MemoryPermission.WRITE);
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_unicornEmu.PC = CodeBaseAddress;
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}
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_unicornEmu = new UnicornAArch64();
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_unicornEmu.MemoryMap(CodeBaseAddress, Size, MemoryPermission.Read | MemoryPermission.Exec);
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_unicornEmu.MemoryMap(DataBaseAddress, Size, MemoryPermission.Read | MemoryPermission.Write);
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_unicornEmu.PC = CodeBaseAddress;
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}
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[TearDown]
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public void Teardown()
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{
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if (_unicornAvailable)
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{
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_unicornEmu.Dispose();
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_unicornEmu = null;
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}
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_unicornEmu.Dispose();
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_unicornEmu = null;
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_memory.DecrementReferenceCount();
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_context.Dispose();
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@ -105,10 +90,7 @@ namespace Ryujinx.Tests.Cpu
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{
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_memory.Write(_currAddress, opcode);
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if (_unicornAvailable)
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{
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_unicornEmu.MemoryWrite32(_currAddress, opcode);
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}
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_unicornEmu.MemoryWrite32(_currAddress, opcode);
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_currAddress += 4;
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}
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@ -158,38 +140,35 @@ namespace Ryujinx.Tests.Cpu
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_context.Fpcr = (FPCR)fpcr;
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_context.Fpsr = (FPSR)fpsr;
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if (_unicornAvailable)
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{
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_unicornEmu.X[0] = x0;
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_unicornEmu.X[1] = x1;
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_unicornEmu.X[2] = x2;
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_unicornEmu.X[3] = x3;
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_unicornEmu.SP = x31;
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_unicornEmu.X[0] = x0;
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_unicornEmu.X[1] = x1;
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_unicornEmu.X[2] = x2;
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_unicornEmu.X[3] = x3;
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_unicornEmu.SP = x31;
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_unicornEmu.Q[0] = V128ToSimdValue(v0);
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_unicornEmu.Q[1] = V128ToSimdValue(v1);
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_unicornEmu.Q[2] = V128ToSimdValue(v2);
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_unicornEmu.Q[3] = V128ToSimdValue(v3);
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_unicornEmu.Q[4] = V128ToSimdValue(v4);
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_unicornEmu.Q[5] = V128ToSimdValue(v5);
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_unicornEmu.Q[30] = V128ToSimdValue(v30);
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_unicornEmu.Q[31] = V128ToSimdValue(v31);
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_unicornEmu.Q[0] = V128ToSimdValue(v0);
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_unicornEmu.Q[1] = V128ToSimdValue(v1);
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_unicornEmu.Q[2] = V128ToSimdValue(v2);
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_unicornEmu.Q[3] = V128ToSimdValue(v3);
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_unicornEmu.Q[4] = V128ToSimdValue(v4);
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_unicornEmu.Q[5] = V128ToSimdValue(v5);
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_unicornEmu.Q[30] = V128ToSimdValue(v30);
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_unicornEmu.Q[31] = V128ToSimdValue(v31);
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_unicornEmu.OverflowFlag = overflow;
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_unicornEmu.CarryFlag = carry;
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_unicornEmu.ZeroFlag = zero;
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_unicornEmu.NegativeFlag = negative;
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_unicornEmu.OverflowFlag = overflow;
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_unicornEmu.CarryFlag = carry;
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_unicornEmu.ZeroFlag = zero;
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_unicornEmu.NegativeFlag = negative;
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_unicornEmu.Fpcr = fpcr;
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_unicornEmu.Fpsr = fpsr;
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}
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_unicornEmu.Fpcr = fpcr;
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_unicornEmu.Fpsr = fpsr;
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}
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protected void ExecuteOpcodes(bool runUnicorn = true)
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{
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_cpuContext.Execute(_context, CodeBaseAddress);
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if (_unicornAvailable && runUnicorn)
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if (runUnicorn)
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{
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_unicornEmu.RunForCount((_currAddress - CodeBaseAddress - 4) / 4);
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}
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@ -239,10 +218,7 @@ namespace Ryujinx.Tests.Cpu
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{
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_memory.Write(DataBaseAddress + offset, data);
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if (_unicornAvailable)
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{
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_unicornEmu.MemoryWrite(DataBaseAddress + offset, data);
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}
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_unicornEmu.MemoryWrite(DataBaseAddress + offset, data);
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_usingMemory = true; // When true, CompareAgainstUnicorn checks the working memory for equality too.
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}
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@ -251,10 +227,7 @@ namespace Ryujinx.Tests.Cpu
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{
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_memory.Write(DataBaseAddress + offset, data);
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if (_unicornAvailable)
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{
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_unicornEmu.MemoryWrite8(DataBaseAddress + offset, data);
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}
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_unicornEmu.MemoryWrite8(DataBaseAddress + offset, data);
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_usingMemory = true; // When true, CompareAgainstUnicorn checks the working memory for equality too.
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}
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@ -331,11 +304,6 @@ namespace Ryujinx.Tests.Cpu
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FpSkips fpSkips = FpSkips.None,
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FpTolerances fpTolerances = FpTolerances.None)
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{
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if (!_unicornAvailable)
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{
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return;
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}
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if (IgnoreAllExcept_FpsrQc)
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{
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fpsrMask &= Fpsr.Qc;
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@ -6,7 +6,6 @@ using Ryujinx.Cpu.Jit;
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using Ryujinx.Memory;
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using Ryujinx.Tests.Unicorn;
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using System;
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using MemoryPermission = Ryujinx.Tests.Unicorn.MemoryPermission;
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namespace Ryujinx.Tests.Cpu
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@ -27,19 +26,10 @@ namespace Ryujinx.Tests.Cpu
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private ExecutionContext _context;
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private CpuContext _cpuContext;
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private static bool _unicornAvailable;
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private UnicornAArch32 _unicornEmu;
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private bool _usingMemory;
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[OneTimeSetUp]
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public void OneTimeSetup()
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{
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_unicornAvailable = UnicornAArch32.IsAvailable();
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Assume.That(_unicornAvailable, "Unicorn is not available");
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}
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[SetUp]
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public void Setup()
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{
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@ -61,23 +51,17 @@ namespace Ryujinx.Tests.Cpu
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Optimizations.AllowLcqInFunctionTable = false;
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Optimizations.UseUnmanagedDispatchLoop = false;
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if (_unicornAvailable)
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{
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_unicornEmu = new UnicornAArch32();
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_unicornEmu.MemoryMap(CodeBaseAddress, Size, MemoryPermission.READ | MemoryPermission.EXEC);
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_unicornEmu.MemoryMap(DataBaseAddress, Size, MemoryPermission.READ | MemoryPermission.WRITE);
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_unicornEmu.PC = CodeBaseAddress;
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}
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_unicornEmu = new UnicornAArch32();
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_unicornEmu.MemoryMap(CodeBaseAddress, Size, MemoryPermission.Read | MemoryPermission.Exec);
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_unicornEmu.MemoryMap(DataBaseAddress, Size, MemoryPermission.Read | MemoryPermission.Write);
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_unicornEmu.PC = CodeBaseAddress;
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}
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[TearDown]
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public void Teardown()
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{
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if (_unicornAvailable)
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{
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_unicornEmu.Dispose();
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_unicornEmu = null;
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}
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_unicornEmu.Dispose();
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_unicornEmu = null;
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_memory.DecrementReferenceCount();
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_context.Dispose();
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@ -101,10 +85,7 @@ namespace Ryujinx.Tests.Cpu
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{
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_memory.Write(_currAddress, opcode);
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if (_unicornAvailable)
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{
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_unicornEmu.MemoryWrite32(_currAddress, opcode);
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}
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_unicornEmu.MemoryWrite32(_currAddress, opcode);
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_currAddress += 4;
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}
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@ -113,10 +94,7 @@ namespace Ryujinx.Tests.Cpu
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{
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_memory.Write(_currAddress, opcode);
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if (_unicornAvailable)
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{
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_unicornEmu.MemoryWrite16(_currAddress, opcode);
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}
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_unicornEmu.MemoryWrite16(_currAddress, opcode);
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_currAddress += 2;
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}
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@ -169,40 +147,37 @@ namespace Ryujinx.Tests.Cpu
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_context.SetPstateFlag(PState.TFlag, thumb);
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if (_unicornAvailable)
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{
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_unicornEmu.R[0] = r0;
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_unicornEmu.R[1] = r1;
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_unicornEmu.R[2] = r2;
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_unicornEmu.R[3] = r3;
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_unicornEmu.SP = sp;
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_unicornEmu.R[0] = r0;
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_unicornEmu.R[1] = r1;
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_unicornEmu.R[2] = r2;
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_unicornEmu.R[3] = r3;
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_unicornEmu.SP = sp;
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_unicornEmu.Q[0] = V128ToSimdValue(v0);
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_unicornEmu.Q[1] = V128ToSimdValue(v1);
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_unicornEmu.Q[2] = V128ToSimdValue(v2);
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_unicornEmu.Q[3] = V128ToSimdValue(v3);
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_unicornEmu.Q[4] = V128ToSimdValue(v4);
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_unicornEmu.Q[5] = V128ToSimdValue(v5);
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_unicornEmu.Q[14] = V128ToSimdValue(v14);
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_unicornEmu.Q[15] = V128ToSimdValue(v15);
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_unicornEmu.Q[0] = V128ToSimdValue(v0);
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_unicornEmu.Q[1] = V128ToSimdValue(v1);
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_unicornEmu.Q[2] = V128ToSimdValue(v2);
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_unicornEmu.Q[3] = V128ToSimdValue(v3);
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_unicornEmu.Q[4] = V128ToSimdValue(v4);
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_unicornEmu.Q[5] = V128ToSimdValue(v5);
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_unicornEmu.Q[14] = V128ToSimdValue(v14);
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_unicornEmu.Q[15] = V128ToSimdValue(v15);
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_unicornEmu.QFlag = saturation;
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_unicornEmu.OverflowFlag = overflow;
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_unicornEmu.CarryFlag = carry;
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_unicornEmu.ZeroFlag = zero;
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_unicornEmu.NegativeFlag = negative;
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_unicornEmu.QFlag = saturation;
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_unicornEmu.OverflowFlag = overflow;
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_unicornEmu.CarryFlag = carry;
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_unicornEmu.ZeroFlag = zero;
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_unicornEmu.NegativeFlag = negative;
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_unicornEmu.Fpscr = fpscr;
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_unicornEmu.Fpscr = fpscr;
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_unicornEmu.ThumbFlag = thumb;
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}
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_unicornEmu.ThumbFlag = thumb;
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}
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protected void ExecuteOpcodes(bool runUnicorn = true)
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{
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_cpuContext.Execute(_context, CodeBaseAddress);
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if (_unicornAvailable && runUnicorn)
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if (runUnicorn)
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{
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_unicornEmu.RunForCount((_currAddress - CodeBaseAddress - 4) / 4);
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}
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@ -322,10 +297,7 @@ namespace Ryujinx.Tests.Cpu
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{
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_memory.Write(DataBaseAddress + offset, data);
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if (_unicornAvailable)
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{
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_unicornEmu.MemoryWrite(DataBaseAddress + offset, data);
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}
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_unicornEmu.MemoryWrite(DataBaseAddress + offset, data);
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_usingMemory = true; // When true, CompareAgainstUnicorn checks the working memory for equality too.
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}
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@ -407,11 +379,6 @@ namespace Ryujinx.Tests.Cpu
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FpSkips fpSkips = FpSkips.None,
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FpTolerances fpTolerances = FpTolerances.None)
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{
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if (!_unicornAvailable)
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{
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return;
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}
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if (fpSkips != FpSkips.None)
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{
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ManageFpSkips(fpSkips);
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@ -1,7 +1,6 @@
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#define Alu
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using NUnit.Framework;
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using System.Collections.Generic;
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namespace Ryujinx.Tests.Cpu
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@ -91,12 +90,10 @@ namespace Ryujinx.Tests.Cpu
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}
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#endregion
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private const int RndCnt = 2;
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[Test, Pairwise, Description("CLS <Xd>, <Xn>")]
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public void Cls_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[ValueSource("_GenLeadingSignsX_")] [Random(RndCnt)] ulong xn)
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[ValueSource(nameof(_GenLeadingSignsX_))] ulong xn)
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{
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uint opcode = 0xDAC01400; // CLS X0, X0
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -111,7 +108,7 @@ namespace Ryujinx.Tests.Cpu
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[Test, Pairwise, Description("CLS <Wd>, <Wn>")]
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public void Cls_32bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[ValueSource("_GenLeadingSignsW_")] [Random(RndCnt)] uint wn)
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[ValueSource(nameof(_GenLeadingSignsW_))] uint wn)
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{
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uint opcode = 0x5AC01400; // CLS W0, W0
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -126,7 +123,7 @@ namespace Ryujinx.Tests.Cpu
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[Test, Pairwise, Description("CLZ <Xd>, <Xn>")]
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public void Clz_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[ValueSource("_GenLeadingZerosX_")] [Random(RndCnt)] ulong xn)
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[ValueSource(nameof(_GenLeadingZerosX_))] ulong xn)
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{
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uint opcode = 0xDAC01000; // CLZ X0, X0
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -141,7 +138,7 @@ namespace Ryujinx.Tests.Cpu
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[Test, Pairwise, Description("CLZ <Wd>, <Wn>")]
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public void Clz_32bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[ValueSource("_GenLeadingZerosW_")] [Random(RndCnt)] uint wn)
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[ValueSource(nameof(_GenLeadingZerosW_))] uint wn)
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{
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uint opcode = 0x5AC01000; // CLZ W0, W0
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -157,7 +154,7 @@ namespace Ryujinx.Tests.Cpu
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public void Rbit_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn)
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn)
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{
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uint opcode = 0xDAC00000; // RBIT X0, X0
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -173,7 +170,7 @@ namespace Ryujinx.Tests.Cpu
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public void Rbit_32bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn)
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0x80000000u, 0xFFFFFFFFu)] uint wn)
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{
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uint opcode = 0x5AC00000; // RBIT W0, W0
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -189,7 +186,7 @@ namespace Ryujinx.Tests.Cpu
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public void Rev16_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn)
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn)
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{
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uint opcode = 0xDAC00400; // REV16 X0, X0
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -205,7 +202,7 @@ namespace Ryujinx.Tests.Cpu
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public void Rev16_32bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
|
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn)
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0x80000000u, 0xFFFFFFFFu)] uint wn)
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{
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uint opcode = 0x5AC00400; // REV16 W0, W0
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -221,7 +218,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Rev32_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn)
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn)
|
||||
{
|
||||
uint opcode = 0xDAC00800; // REV32 X0, X0
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -237,7 +234,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Rev32_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn)
|
||||
{
|
||||
uint opcode = 0x5AC00800; // REV W0, W0
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -253,7 +250,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Rev64_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn)
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn)
|
||||
{
|
||||
uint opcode = 0xDAC00C00; // REV64 X0, X0
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -266,4 +263,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -12,7 +12,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Opcodes)"
|
||||
private static uint[] _SU_H_AddSub_8_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xe6100f90u, // SADD8 R0, R0, R0
|
||||
0xe6100ff0u, // SSUB8 R0, R0, R0
|
||||
@ -27,7 +27,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Ssat_Usat_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xe6a00010u, // SSAT R0, #1, R0, LSL #0
|
||||
0xe6a00050u, // SSAT R0, #1, R0, ASR #32
|
||||
@ -38,7 +38,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Ssat16_Usat16_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xe6a00f30u, // SSAT16 R0, #1, R0
|
||||
0xe6e00f30u, // USAT16 R0, #0, R0
|
||||
@ -47,7 +47,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Lsr_Lsl_Asr_Ror_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xe1b00030u, // LSRS R0, R0, R0
|
||||
0xe1b00010u, // LSLS R0, R0, R0
|
||||
@ -63,7 +63,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Rbit_32bit([Values(0u, 0xdu)] uint rd,
|
||||
[Values(1u, 0xdu)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn)
|
||||
{
|
||||
uint opcode = 0xe6ff0f30u; // RBIT R0, R0
|
||||
opcode |= ((rm & 15) << 0) | ((rd & 15) << 12);
|
||||
@ -76,10 +76,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Lsr_Lsl_Asr_Ror([ValueSource("_Lsr_Lsl_Asr_Ror_")] uint opcode,
|
||||
public void Lsr_Lsl_Asr_Ror([ValueSource(nameof(_Lsr_Lsl_Asr_Ror_))] uint opcode,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint shiftValue,
|
||||
[Range(0, 31)] [Values(32, 256, 768, -1, -23)] int shiftAmount)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint shiftValue,
|
||||
[Range(0, 31)] int shiftAmount)
|
||||
{
|
||||
uint rd = 0;
|
||||
uint rm = 1;
|
||||
@ -130,13 +130,13 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Ssat_Usat([ValueSource("_Ssat_Usat_")] uint opcode,
|
||||
public void Ssat_Usat([ValueSource(nameof(_Ssat_Usat_))] uint opcode,
|
||||
[Values(0u, 0xdu)] uint rd,
|
||||
[Values(1u, 0xdu)] uint rn,
|
||||
[Values(0u, 7u, 8u, 0xfu, 0x10u, 0x1fu)] uint sat,
|
||||
[Values(0u, 7u, 8u, 0xfu, 0x10u, 0x1fu)] uint shift,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn)
|
||||
{
|
||||
opcode |= ((rn & 15) << 0) | ((shift & 31) << 7) | ((rd & 15) << 12) | ((sat & 31) << 16);
|
||||
|
||||
@ -148,12 +148,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Ssat16_Usat16([ValueSource("_Ssat16_Usat16_")] uint opcode,
|
||||
public void Ssat16_Usat16([ValueSource(nameof(_Ssat16_Usat16_))] uint opcode,
|
||||
[Values(0u, 0xdu)] uint rd,
|
||||
[Values(1u, 0xdu)] uint rn,
|
||||
[Values(0u, 7u, 8u, 0xfu)] uint sat,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn)
|
||||
{
|
||||
opcode |= ((rn & 15) << 0) | ((rd & 15) << 12) | ((sat & 15) << 16);
|
||||
|
||||
@ -165,7 +165,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void SU_H_AddSub_8([ValueSource("_SU_H_AddSub_8_")] uint opcode,
|
||||
public void SU_H_AddSub_8([ValueSource(nameof(_SU_H_AddSub_8_))] uint opcode,
|
||||
[Values(0u, 0xdu)] uint rd,
|
||||
[Values(1u)] uint rm,
|
||||
[Values(2u)] uint rn,
|
||||
@ -206,4 +206,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -36,7 +36,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
// - xor 0
|
||||
// Only includes non-C variant, as the other can be tested with unicorn.
|
||||
|
||||
return new CrcTest[]
|
||||
return new[]
|
||||
{
|
||||
new CrcTest(0x00000000u, 0x00_00_00_00_00_00_00_00u, false, 0x00000000, 0x00000000, 0x00000000, 0x00000000),
|
||||
new CrcTest(0x00000000u, 0x7f_ff_ff_ff_ff_ff_ff_ffu, false, 0x2d02ef8d, 0xbe2612ff, 0xdebb20e3, 0xa9de8355),
|
||||
@ -53,14 +53,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endregion
|
||||
|
||||
private const int RndCnt = 2;
|
||||
|
||||
[Test, Combinatorial]
|
||||
public void Crc32_b_h_w_x([Values(0u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[Values(2u)] uint rm,
|
||||
[Range(0u, 3u)] uint size,
|
||||
[ValueSource("_CRC32_Test_Values_")] CrcTest test)
|
||||
[ValueSource(nameof(_CRC32_Test_Values_))] CrcTest test)
|
||||
{
|
||||
uint opcode = 0x1AC04000; // CRC32B W0, W0, W0
|
||||
|
||||
@ -85,11 +83,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Crc32x([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values((ulong)0x00_00_00_00_00_00_00_00,
|
||||
(ulong)0x7F_FF_FF_FF_FF_FF_FF_FF,
|
||||
(ulong)0x80_00_00_00_00_00_00_00,
|
||||
(ulong)0xFF_FF_FF_FF_FF_FF_FF_FF)] [Random(RndCnt)] ulong xm)
|
||||
0x80_00_00_00_00_00_00_00,
|
||||
0xFF_FF_FF_FF_FF_FF_FF_FF)] ulong xm)
|
||||
{
|
||||
uint opcode = 0x9AC04C00; // CRC32X W0, W0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -105,9 +103,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Crc32w([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values((uint)0x00_00_00_00, (uint)0x7F_FF_FF_FF,
|
||||
(uint)0x80_00_00_00, (uint)0xFF_FF_FF_FF)] [Random(RndCnt)] uint wm)
|
||||
0x80_00_00_00, 0xFF_FF_FF_FF)] uint wm)
|
||||
{
|
||||
uint opcode = 0x1AC04800; // CRC32W W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -123,9 +121,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Crc32h([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values((ushort)0x00_00, (ushort)0x7F_FF,
|
||||
(ushort)0x80_00, (ushort)0xFF_FF)] [Random(RndCnt)] ushort wm)
|
||||
(ushort)0x80_00, (ushort)0xFF_FF)] ushort wm)
|
||||
{
|
||||
uint opcode = 0x1AC04400; // CRC32H W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -141,9 +139,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Crc32b([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values((byte)0x00, (byte)0x7F,
|
||||
(byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm)
|
||||
(byte)0x80, (byte)0xFF)] byte wm)
|
||||
{
|
||||
uint opcode = 0x1AC04000; // CRC32B W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -159,11 +157,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Crc32cx([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values((ulong)0x00_00_00_00_00_00_00_00,
|
||||
(ulong)0x7F_FF_FF_FF_FF_FF_FF_FF,
|
||||
(ulong)0x80_00_00_00_00_00_00_00,
|
||||
(ulong)0xFF_FF_FF_FF_FF_FF_FF_FF)] [Random(RndCnt)] ulong xm)
|
||||
0x80_00_00_00_00_00_00_00,
|
||||
0xFF_FF_FF_FF_FF_FF_FF_FF)] ulong xm)
|
||||
{
|
||||
uint opcode = 0x9AC05C00; // CRC32CX W0, W0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -179,9 +177,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Crc32cw([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values((uint)0x00_00_00_00, (uint)0x7F_FF_FF_FF,
|
||||
(uint)0x80_00_00_00, (uint)0xFF_FF_FF_FF)] [Random(RndCnt)] uint wm)
|
||||
0x80_00_00_00, 0xFF_FF_FF_FF)] uint wm)
|
||||
{
|
||||
uint opcode = 0x1AC05800; // CRC32CW W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -197,9 +195,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Crc32ch([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values((ushort)0x00_00, (ushort)0x7F_FF,
|
||||
(ushort)0x80_00, (ushort)0xFF_FF)] [Random(RndCnt)] ushort wm)
|
||||
(ushort)0x80_00, (ushort)0xFF_FF)] ushort wm)
|
||||
{
|
||||
uint opcode = 0x1AC05400; // CRC32CH W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -215,9 +213,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Crc32cb([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0x00000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values((byte)0x00, (byte)0x7F,
|
||||
(byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm)
|
||||
(byte)0x80, (byte)0xFF)] byte wm)
|
||||
{
|
||||
uint opcode = 0x1AC05000; // CRC32CB W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -234,9 +232,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm)
|
||||
{
|
||||
uint opcode = 0x9AC00C00; // SDIV X0, X0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -253,9 +251,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm)
|
||||
{
|
||||
uint opcode = 0x1AC00C00; // SDIV W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -272,9 +270,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm)
|
||||
{
|
||||
uint opcode = 0x9AC00800; // UDIV X0, X0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -291,9 +289,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm)
|
||||
{
|
||||
uint opcode = 0x1AC00800; // UDIV W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -306,4 +304,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -36,7 +36,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
// - bytes in order of increasing significance
|
||||
// - xor 0
|
||||
|
||||
return new CrcTest32[]
|
||||
return new[]
|
||||
{
|
||||
new CrcTest32(0x00000000u, 0x00_00_00_00u, false, 0x00000000, 0x00000000, 0x00000000),
|
||||
new CrcTest32(0x00000000u, 0x7f_ff_ff_ffu, false, 0x2d02ef8d, 0xbe2612ff, 0x3303a3c3),
|
||||
@ -70,7 +70,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u)] uint rn,
|
||||
[Values(2u)] uint rm,
|
||||
[Range(0u, 2u)] uint size,
|
||||
[ValueSource("_CRC32_Test_Values_")] CrcTest32 test)
|
||||
[ValueSource(nameof(_CRC32_Test_Values_))] CrcTest32 test)
|
||||
{
|
||||
// Unicorn does not yet support 32bit crc instructions, so test against a known table of results/values.
|
||||
|
||||
|
||||
@ -8,17 +8,13 @@ namespace Ryujinx.Tests.Cpu
|
||||
public sealed class CpuTestAluImm : CpuTest
|
||||
{
|
||||
#if AluImm
|
||||
private const int RndCnt = 2;
|
||||
private const int RndCntImm = 2;
|
||||
private const int RndCntImms = 2;
|
||||
private const int RndCntImmr = 2;
|
||||
|
||||
[Test, Pairwise, Description("ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}")]
|
||||
public void Add_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
|
||||
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
|
||||
[Values(0u, 4095u)] uint imm,
|
||||
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
|
||||
{
|
||||
uint opcode = 0x91000000; // ADD X0, X0, #0, LSL #0
|
||||
@ -41,8 +37,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Add_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
|
||||
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
|
||||
[Values(0u, 4095u)] uint imm,
|
||||
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
|
||||
{
|
||||
uint opcode = 0x11000000; // ADD W0, W0, #0, LSL #0
|
||||
@ -65,8 +61,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Adds_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
|
||||
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
|
||||
[Values(0u, 4095u)] uint imm,
|
||||
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
|
||||
{
|
||||
uint opcode = 0xB1000000; // ADDS X0, X0, #0, LSL #0
|
||||
@ -89,8 +85,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Adds_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
|
||||
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
|
||||
[Values(0u, 4095u)] uint imm,
|
||||
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
|
||||
{
|
||||
uint opcode = 0x31000000; // ADDS W0, W0, #0, LSL #0
|
||||
@ -113,9 +109,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void And_N1_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
[Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // <imm>
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // <imm>
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0u, 31u, 32u, 62u)] uint imms, // <imm>
|
||||
[Values(0u, 31u, 32u, 63u)] uint immr) // <imm>
|
||||
{
|
||||
uint opcode = 0x92400000; // AND X0, X0, #0x1
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -132,9 +128,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void And_N0_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
|
||||
[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
|
||||
{
|
||||
uint opcode = 0x92000000; // AND X0, X0, #0x100000001
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -151,9 +147,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void And_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
|
||||
[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
|
||||
{
|
||||
uint opcode = 0x12000000; // AND W0, W0, #0x1
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -170,9 +166,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Ands_N1_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
[Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // <imm>
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // <imm>
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0u, 31u, 32u, 62u)] uint imms, // <imm>
|
||||
[Values(0u, 31u, 32u, 63u)] uint immr) // <imm>
|
||||
{
|
||||
uint opcode = 0xF2400000; // ANDS X0, X0, #0x1
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -189,9 +185,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Ands_N0_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
|
||||
[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
|
||||
{
|
||||
uint opcode = 0xF2000000; // ANDS X0, X0, #0x100000001
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -208,9 +204,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Ands_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
|
||||
[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
|
||||
{
|
||||
uint opcode = 0x72000000; // ANDS W0, W0, #0x1
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -227,9 +223,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Eor_N1_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
[Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // <imm>
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // <imm>
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0u, 31u, 32u, 62u)] uint imms, // <imm>
|
||||
[Values(0u, 31u, 32u, 63u)] uint immr) // <imm>
|
||||
{
|
||||
uint opcode = 0xD2400000; // EOR X0, X0, #0x1
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -246,9 +242,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Eor_N0_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
|
||||
[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
|
||||
{
|
||||
uint opcode = 0xD2000000; // EOR X0, X0, #0x100000001
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -265,9 +261,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Eor_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
|
||||
[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
|
||||
{
|
||||
uint opcode = 0x52000000; // EOR W0, W0, #0x1
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -284,9 +280,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Orr_N1_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
[Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // <imm>
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // <imm>
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0u, 31u, 32u, 62u)] uint imms, // <imm>
|
||||
[Values(0u, 31u, 32u, 63u)] uint immr) // <imm>
|
||||
{
|
||||
uint opcode = 0xB2400000; // ORR X0, X0, #0x1
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -303,9 +299,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Orr_N0_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
|
||||
[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
|
||||
{
|
||||
uint opcode = 0xB2000000; // ORR X0, X0, #0x100000001
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -322,9 +318,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Orr_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
|
||||
[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
|
||||
{
|
||||
uint opcode = 0x32000000; // ORR W0, W0, #0x1
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -341,8 +337,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Sub_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
|
||||
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
|
||||
[Values(0u, 4095u)] uint imm,
|
||||
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
|
||||
{
|
||||
uint opcode = 0xD1000000; // SUB X0, X0, #0, LSL #0
|
||||
@ -365,8 +361,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Sub_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
|
||||
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
|
||||
[Values(0u, 4095u)] uint imm,
|
||||
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
|
||||
{
|
||||
uint opcode = 0x51000000; // SUB W0, W0, #0, LSL #0
|
||||
@ -389,8 +385,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Subs_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
|
||||
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
|
||||
[Values(0u, 4095u)] uint imm,
|
||||
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
|
||||
{
|
||||
uint opcode = 0xF1000000; // SUBS X0, X0, #0, LSL #0
|
||||
@ -413,8 +409,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Subs_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
|
||||
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
|
||||
[Values(0u, 4095u)] uint imm,
|
||||
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
|
||||
{
|
||||
uint opcode = 0x71000000; // SUBS W0, W0, #0, LSL #0
|
||||
@ -434,4 +430,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -12,7 +12,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Opcodes)"
|
||||
private static uint[] _opcodes()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xe2a00000u, // ADC R0, R0, #0
|
||||
0xe2b00000u, // ADCS R0, R0, #0
|
||||
@ -33,10 +33,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
#endregion
|
||||
|
||||
private const int RndCnt = 2;
|
||||
private const int RndCntAmount = 2;
|
||||
|
||||
[Test, Pairwise]
|
||||
public void TestCpuTestAluImm32([ValueSource("_opcodes")] uint opcode,
|
||||
public void TestCpuTestAluImm32([ValueSource(nameof(_opcodes))] uint opcode,
|
||||
[Values(0u, 13u)] uint rd,
|
||||
[Values(1u, 13u)] uint rn,
|
||||
[Random(RndCnt)] uint imm,
|
||||
@ -53,4 +52,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -8,18 +8,15 @@ namespace Ryujinx.Tests.Cpu
|
||||
public sealed class CpuTestAluRs : CpuTest
|
||||
{
|
||||
#if AluRs
|
||||
private const int RndCnt = 2;
|
||||
private const int RndCntAmount = 2;
|
||||
private const int RndCntLsb = 2;
|
||||
|
||||
[Test, Pairwise, Description("ADC <Xd>, <Xn>, <Xm>")]
|
||||
public void Adc_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values] bool carryIn)
|
||||
{
|
||||
uint opcode = 0x9A000000; // ADC X0, X0, X0
|
||||
@ -37,9 +34,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values] bool carryIn)
|
||||
{
|
||||
uint opcode = 0x1A000000; // ADC W0, W0, W0
|
||||
@ -57,9 +54,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values] bool carryIn)
|
||||
{
|
||||
uint opcode = 0xBA000000; // ADCS X0, X0, X0
|
||||
@ -77,9 +74,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values] bool carryIn)
|
||||
{
|
||||
uint opcode = 0x3A000000; // ADCS W0, W0, W0
|
||||
@ -97,11 +94,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint shift, // <LSL, LSR, ASR>
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 31u, 32u, 63u)] uint amount)
|
||||
{
|
||||
uint opcode = 0x8B000000; // ADD X0, X0, X0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -119,11 +116,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint shift, // <LSL, LSR, ASR>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 15u, 16u, 31u)] uint amount)
|
||||
{
|
||||
uint opcode = 0x0B000000; // ADD W0, W0, W0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -141,11 +138,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint shift, // <LSL, LSR, ASR>
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 31u, 32u, 63u)] uint amount)
|
||||
{
|
||||
uint opcode = 0xAB000000; // ADDS X0, X0, X0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -163,11 +160,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint shift, // <LSL, LSR, ASR>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 15u, 16u, 31u)] uint amount)
|
||||
{
|
||||
uint opcode = 0x2B000000; // ADDS W0, W0, W0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -185,11 +182,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR>
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 31u, 32u, 63u)] uint amount)
|
||||
{
|
||||
uint opcode = 0x8A000000; // AND X0, X0, X0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -207,11 +204,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 15u, 16u, 31u)] uint amount)
|
||||
{
|
||||
uint opcode = 0x0A000000; // AND W0, W0, W0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -229,11 +226,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR>
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 31u, 32u, 63u)] uint amount)
|
||||
{
|
||||
uint opcode = 0xEA000000; // ANDS X0, X0, X0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -251,11 +248,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 15u, 16u, 31u)] uint amount)
|
||||
{
|
||||
uint opcode = 0x6A000000; // ANDS W0, W0, W0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -273,9 +270,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm)
|
||||
{
|
||||
uint opcode = 0x9AC02800; // ASRV X0, X0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -292,9 +289,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm)
|
||||
{
|
||||
uint opcode = 0x1AC02800; // ASRV W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -311,11 +308,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR>
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 31u, 32u, 63u)] uint amount)
|
||||
{
|
||||
uint opcode = 0x8A200000; // BIC X0, X0, X0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -333,11 +330,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 15u, 16u, 31u)] uint amount)
|
||||
{
|
||||
uint opcode = 0x0A200000; // BIC W0, W0, W0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -355,11 +352,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR>
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 31u, 32u, 63u)] uint amount)
|
||||
{
|
||||
uint opcode = 0xEA200000; // BICS X0, X0, X0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -377,11 +374,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 15u, 16u, 31u)] uint amount)
|
||||
{
|
||||
uint opcode = 0x6A200000; // BICS W0, W0, W0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -399,11 +396,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR>
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 31u, 32u, 63u)] uint amount)
|
||||
{
|
||||
uint opcode = 0xCA200000; // EON X0, X0, X0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -421,11 +418,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 15u, 16u, 31u)] uint amount)
|
||||
{
|
||||
uint opcode = 0x4A200000; // EON W0, W0, W0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -443,11 +440,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR>
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 31u, 32u, 63u)] uint amount)
|
||||
{
|
||||
uint opcode = 0xCA000000; // EOR X0, X0, X0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -465,11 +462,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 15u, 16u, 31u)] uint amount)
|
||||
{
|
||||
uint opcode = 0x4A000000; // EOR W0, W0, W0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -487,10 +484,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntLsb)] uint lsb)
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values(0u, 31u, 32u, 63u)] uint lsb)
|
||||
{
|
||||
uint opcode = 0x93C00000; // EXTR X0, X0, X0, #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -508,10 +505,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntLsb)] uint lsb)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0u, 15u, 16u, 31u)] uint lsb)
|
||||
{
|
||||
uint opcode = 0x13800000; // EXTR W0, W0, W0, #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -529,9 +526,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm)
|
||||
{
|
||||
uint opcode = 0x9AC02000; // LSLV X0, X0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -548,9 +545,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm)
|
||||
{
|
||||
uint opcode = 0x1AC02000; // LSLV W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -567,9 +564,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm)
|
||||
{
|
||||
uint opcode = 0x9AC02400; // LSRV X0, X0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -586,9 +583,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm)
|
||||
{
|
||||
uint opcode = 0x1AC02400; // LSRV W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -605,11 +602,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR>
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 31u, 32u, 63u)] uint amount)
|
||||
{
|
||||
uint opcode = 0xAA200000; // ORN X0, X0, X0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -627,11 +624,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 15u, 16u, 31u)] uint amount)
|
||||
{
|
||||
uint opcode = 0x2A200000; // ORN W0, W0, W0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -649,11 +646,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR>
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 31u, 32u, 63u)] uint amount)
|
||||
{
|
||||
uint opcode = 0xAA000000; // ORR X0, X0, X0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -671,11 +668,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 15u, 16u, 31u)] uint amount)
|
||||
{
|
||||
uint opcode = 0x2A000000; // ORR W0, W0, W0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -693,9 +690,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm)
|
||||
{
|
||||
uint opcode = 0x9AC02C00; // RORV X0, X0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -712,9 +709,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm)
|
||||
{
|
||||
uint opcode = 0x1AC02C00; // RORV W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -731,9 +728,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values] bool carryIn)
|
||||
{
|
||||
uint opcode = 0xDA000000; // SBC X0, X0, X0
|
||||
@ -751,9 +748,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values] bool carryIn)
|
||||
{
|
||||
uint opcode = 0x5A000000; // SBC W0, W0, W0
|
||||
@ -771,9 +768,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values] bool carryIn)
|
||||
{
|
||||
uint opcode = 0xFA000000; // SBCS X0, X0, X0
|
||||
@ -791,9 +788,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values] bool carryIn)
|
||||
{
|
||||
uint opcode = 0x7A000000; // SBCS W0, W0, W0
|
||||
@ -811,11 +808,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint shift, // <LSL, LSR, ASR>
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 31u, 32u, 63u)] uint amount)
|
||||
{
|
||||
uint opcode = 0xCB000000; // SUB X0, X0, X0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -833,11 +830,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint shift, // <LSL, LSR, ASR>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 15u, 16u, 31u)] uint amount)
|
||||
{
|
||||
uint opcode = 0x4B000000; // SUB W0, W0, W0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -855,11 +852,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint shift, // <LSL, LSR, ASR>
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 31u, 32u, 63u)] uint amount)
|
||||
{
|
||||
uint opcode = 0xEB000000; // SUBS X0, X0, X0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -877,11 +874,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint shift, // <LSL, LSR, ASR>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 15u, 16u, 31u)] uint amount)
|
||||
{
|
||||
uint opcode = 0x6B000000; // SUBS W0, W0, W0, LSL #0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -895,4 +892,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -12,7 +12,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Opcodes)"
|
||||
private static uint[] _Add_Adds_Rsb_Rsbs_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xe0800000u, // ADD R0, R0, R0, LSL #0
|
||||
0xe0900000u, // ADDS R0, R0, R0, LSL #0
|
||||
@ -23,7 +23,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Adc_Adcs_Rsc_Rscs_Sbc_Sbcs_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xe0a00000u, // ADC R0, R0, R0
|
||||
0xe0b00000u, // ADCS R0, R0, R0
|
||||
@ -35,8 +35,6 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endregion
|
||||
|
||||
private const int RndCnt = 2;
|
||||
private const int RndCntAmount = 2;
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Adc_Adcs_Rsc_Rscs_Sbc_Sbcs([ValueSource("_Adc_Adcs_Rsc_Rscs_Sbc_Sbcs_")] uint opcode,
|
||||
@ -44,9 +42,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 13u)] uint rn,
|
||||
[Values(2u, 13u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values] bool carryIn)
|
||||
{
|
||||
opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12);
|
||||
@ -64,11 +62,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 13u)] uint rn,
|
||||
[Values(2u, 13u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
|
||||
[Values(0u, 15u, 16u, 31u)] uint amount)
|
||||
{
|
||||
opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12);
|
||||
opcode |= ((shift & 3) << 5) | ((amount & 31) << 7);
|
||||
@ -81,4 +79,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -8,16 +8,15 @@ namespace Ryujinx.Tests.Cpu
|
||||
public sealed class CpuTestAluRx : CpuTest
|
||||
{
|
||||
#if AluRx
|
||||
private const int RndCnt = 2;
|
||||
|
||||
[Test, Pairwise, Description("ADD <Xd|SP>, <Xn|SP>, <X><m>{, <extend> {#<amount>}}")]
|
||||
public void Add_X_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
|
||||
[Values((ulong)0x0000000000000000, (ulong)0x7FFFFFFFFFFFFFFF,
|
||||
(ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000, 0xFFFFFFFFFFFFFFFF)] ulong xm,
|
||||
[Values(0b011u, 0b111u)] uint extend, // <LSL|UXTX, SXTX>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
{
|
||||
@ -44,9 +43,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
|
||||
[Values((uint)0x00000000, (uint)0x7FFFFFFF,
|
||||
(uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint wm,
|
||||
0x80000000, 0xFFFFFFFF)] uint wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, // <UXTB, UXTH, UXTW,
|
||||
0b100u, 0b101u, 0b110u)] uint extend, // SXTB, SXTH, SXTW>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -74,9 +73,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
|
||||
[Values((ushort)0x0000, (ushort)0x7FFF,
|
||||
(ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort wm,
|
||||
(ushort)0x8000, (ushort)0xFFFF)] ushort wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, // <UXTB, UXTH, UXTW,
|
||||
0b100u, 0b101u, 0b110u)] uint extend, // SXTB, SXTH, SXTW>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -104,9 +103,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
|
||||
[Values((byte)0x00, (byte)0x7F,
|
||||
(byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm,
|
||||
(byte)0x80, (byte)0xFF)] byte wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, // <UXTB, UXTH, UXTW,
|
||||
0b100u, 0b101u, 0b110u)] uint extend, // SXTB, SXTH, SXTW>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -134,9 +133,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
|
||||
[Values((uint)0x00000000, (uint)0x7FFFFFFF,
|
||||
(uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint wm,
|
||||
0x80000000, 0xFFFFFFFF)] uint wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, 0b011u, // <UXTB, UXTH, LSL|UXTW, UXTX,
|
||||
0b100u, 0b101u, 0b110u, 0b111u)] uint extend, // SXTB, SXTH, SXTW, SXTX>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -164,9 +163,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
|
||||
[Values((ushort)0x0000, (ushort)0x7FFF,
|
||||
(ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort wm,
|
||||
(ushort)0x8000, (ushort)0xFFFF)] ushort wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, 0b011u, // <UXTB, UXTH, LSL|UXTW, UXTX,
|
||||
0b100u, 0b101u, 0b110u, 0b111u)] uint extend, // SXTB, SXTH, SXTW, SXTX>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -194,9 +193,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
|
||||
[Values((byte)0x00, (byte)0x7F,
|
||||
(byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm,
|
||||
(byte)0x80, (byte)0xFF)] byte wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, 0b011u, // <UXTB, UXTH, LSL|UXTW, UXTX,
|
||||
0b100u, 0b101u, 0b110u, 0b111u)] uint extend, // SXTB, SXTH, SXTW, SXTX>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -224,9 +223,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
|
||||
[Values((ulong)0x0000000000000000, (ulong)0x7FFFFFFFFFFFFFFF,
|
||||
(ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000, 0xFFFFFFFFFFFFFFFF)] ulong xm,
|
||||
[Values(0b011u, 0b111u)] uint extend, // <LSL|UXTX, SXTX>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
{
|
||||
@ -244,9 +243,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
|
||||
[Values((uint)0x00000000, (uint)0x7FFFFFFF,
|
||||
(uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint wm,
|
||||
0x80000000, 0xFFFFFFFF)] uint wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, // <UXTB, UXTH, UXTW,
|
||||
0b100u, 0b101u, 0b110u)] uint extend, // SXTB, SXTH, SXTW>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -265,9 +264,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
|
||||
[Values((ushort)0x0000, (ushort)0x7FFF,
|
||||
(ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort wm,
|
||||
(ushort)0x8000, (ushort)0xFFFF)] ushort wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, // <UXTB, UXTH, UXTW,
|
||||
0b100u, 0b101u, 0b110u)] uint extend, // SXTB, SXTH, SXTW>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -286,9 +285,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
|
||||
[Values((byte)0x00, (byte)0x7F,
|
||||
(byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm,
|
||||
(byte)0x80, (byte)0xFF)] byte wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, // <UXTB, UXTH, UXTW,
|
||||
0b100u, 0b101u, 0b110u)] uint extend, // SXTB, SXTH, SXTW>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -307,9 +306,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
|
||||
[Values((uint)0x00000000, (uint)0x7FFFFFFF,
|
||||
(uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint wm,
|
||||
0x80000000, 0xFFFFFFFF)] uint wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, 0b011u, // <UXTB, UXTH, LSL|UXTW, UXTX,
|
||||
0b100u, 0b101u, 0b110u, 0b111u)] uint extend, // SXTB, SXTH, SXTW, SXTX>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -328,9 +327,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
|
||||
[Values((ushort)0x0000, (ushort)0x7FFF,
|
||||
(ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort wm,
|
||||
(ushort)0x8000, (ushort)0xFFFF)] ushort wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, 0b011u, // <UXTB, UXTH, LSL|UXTW, UXTX,
|
||||
0b100u, 0b101u, 0b110u, 0b111u)] uint extend, // SXTB, SXTH, SXTW, SXTX>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -349,9 +348,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
|
||||
[Values((byte)0x00, (byte)0x7F,
|
||||
(byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm,
|
||||
(byte)0x80, (byte)0xFF)] byte wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, 0b011u, // <UXTB, UXTH, LSL|UXTW, UXTX,
|
||||
0b100u, 0b101u, 0b110u, 0b111u)] uint extend, // SXTB, SXTH, SXTW, SXTX>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -370,9 +369,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
|
||||
[Values((ulong)0x0000000000000000, (ulong)0x7FFFFFFFFFFFFFFF,
|
||||
(ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000, 0xFFFFFFFFFFFFFFFF)] ulong xm,
|
||||
[Values(0b011u, 0b111u)] uint extend, // <LSL|UXTX, SXTX>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
{
|
||||
@ -399,9 +398,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
|
||||
[Values((uint)0x00000000, (uint)0x7FFFFFFF,
|
||||
(uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint wm,
|
||||
0x80000000, 0xFFFFFFFF)] uint wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, // <UXTB, UXTH, UXTW,
|
||||
0b100u, 0b101u, 0b110u)] uint extend, // SXTB, SXTH, SXTW>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -429,9 +428,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
|
||||
[Values((ushort)0x0000, (ushort)0x7FFF,
|
||||
(ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort wm,
|
||||
(ushort)0x8000, (ushort)0xFFFF)] ushort wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, // <UXTB, UXTH, UXTW,
|
||||
0b100u, 0b101u, 0b110u)] uint extend, // SXTB, SXTH, SXTW>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -459,9 +458,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
|
||||
[Values((byte)0x00, (byte)0x7F,
|
||||
(byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm,
|
||||
(byte)0x80, (byte)0xFF)] byte wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, // <UXTB, UXTH, UXTW,
|
||||
0b100u, 0b101u, 0b110u)] uint extend, // SXTB, SXTH, SXTW>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -489,9 +488,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
|
||||
[Values((uint)0x00000000, (uint)0x7FFFFFFF,
|
||||
(uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint wm,
|
||||
0x80000000, 0xFFFFFFFF)] uint wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, 0b011u, // <UXTB, UXTH, LSL|UXTW, UXTX,
|
||||
0b100u, 0b101u, 0b110u, 0b111u)] uint extend, // SXTB, SXTH, SXTW, SXTX>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -519,9 +518,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
|
||||
[Values((ushort)0x0000, (ushort)0x7FFF,
|
||||
(ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort wm,
|
||||
(ushort)0x8000, (ushort)0xFFFF)] ushort wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, 0b011u, // <UXTB, UXTH, LSL|UXTW, UXTX,
|
||||
0b100u, 0b101u, 0b110u, 0b111u)] uint extend, // SXTB, SXTH, SXTW, SXTX>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -549,9 +548,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
|
||||
[Values((byte)0x00, (byte)0x7F,
|
||||
(byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm,
|
||||
(byte)0x80, (byte)0xFF)] byte wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, 0b011u, // <UXTB, UXTH, LSL|UXTW, UXTX,
|
||||
0b100u, 0b101u, 0b110u, 0b111u)] uint extend, // SXTB, SXTH, SXTW, SXTX>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -579,9 +578,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
|
||||
[Values((ulong)0x0000000000000000, (ulong)0x7FFFFFFFFFFFFFFF,
|
||||
(ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000, 0xFFFFFFFFFFFFFFFF)] ulong xm,
|
||||
[Values(0b011u, 0b111u)] uint extend, // <LSL|UXTX, SXTX>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
{
|
||||
@ -599,9 +598,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
|
||||
[Values((uint)0x00000000, (uint)0x7FFFFFFF,
|
||||
(uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint wm,
|
||||
0x80000000, 0xFFFFFFFF)] uint wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, // <UXTB, UXTH, UXTW,
|
||||
0b100u, 0b101u, 0b110u)] uint extend, // SXTB, SXTH, SXTW>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -620,9 +619,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
|
||||
[Values((ushort)0x0000, (ushort)0x7FFF,
|
||||
(ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort wm,
|
||||
(ushort)0x8000, (ushort)0xFFFF)] ushort wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, // <UXTB, UXTH, UXTW,
|
||||
0b100u, 0b101u, 0b110u)] uint extend, // SXTB, SXTH, SXTW>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -641,9 +640,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
|
||||
[Values((byte)0x00, (byte)0x7F,
|
||||
(byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm,
|
||||
(byte)0x80, (byte)0xFF)] byte wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, // <UXTB, UXTH, UXTW,
|
||||
0b100u, 0b101u, 0b110u)] uint extend, // SXTB, SXTH, SXTW>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -662,9 +661,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
|
||||
[Values((uint)0x00000000, (uint)0x7FFFFFFF,
|
||||
(uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint wm,
|
||||
0x80000000, 0xFFFFFFFF)] uint wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, 0b011u, // <UXTB, UXTH, LSL|UXTW, UXTX,
|
||||
0b100u, 0b101u, 0b110u, 0b111u)] uint extend, // SXTB, SXTH, SXTW, SXTX>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -683,9 +682,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
|
||||
[Values((ushort)0x0000, (ushort)0x7FFF,
|
||||
(ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort wm,
|
||||
(ushort)0x8000, (ushort)0xFFFF)] ushort wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, 0b011u, // <UXTB, UXTH, LSL|UXTW, UXTX,
|
||||
0b100u, 0b101u, 0b110u, 0b111u)] uint extend, // SXTB, SXTH, SXTW, SXTX>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -704,9 +703,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
|
||||
[Values((byte)0x00, (byte)0x7F,
|
||||
(byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm,
|
||||
(byte)0x80, (byte)0xFF)] byte wm,
|
||||
[Values(0b000u, 0b001u, 0b010u, 0b011u, // <UXTB, UXTH, LSL|UXTW, UXTX,
|
||||
0b100u, 0b101u, 0b110u, 0b111u)] uint extend, // SXTB, SXTH, SXTW, SXTX>
|
||||
[Values(0u, 1u, 2u, 3u, 4u)] uint amount)
|
||||
@ -721,4 +720,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -10,15 +10,13 @@ namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
#if Bf32
|
||||
private const int RndCnt = 2;
|
||||
private const int RndCntImmr = 2;
|
||||
private const int RndCntImms = 2;
|
||||
|
||||
[Test, Pairwise, Description("BFC <Rd>, #<lsb>, #<width>")]
|
||||
public void Bfc([Values(0u, 0xdu)] uint rd,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wd,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint lsb,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint msb)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wd,
|
||||
[Values(0u, 15u, 16u, 31u)] uint lsb,
|
||||
[Values(0u, 15u, 16u, 31u)] uint msb)
|
||||
{
|
||||
msb = Math.Max(lsb, msb); // Don't test unpredictable for now.
|
||||
uint opcode = 0xe7c0001fu; // BFC R0, #0, #1
|
||||
@ -37,9 +35,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 0xdu)] uint rn,
|
||||
[Random(RndCnt)] uint wd,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint lsb,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint msb)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0u, 15u, 16u, 31u)] uint lsb,
|
||||
[Values(0u, 15u, 16u, 31u)] uint msb)
|
||||
{
|
||||
msb = Math.Max(lsb, msb); // Don't test unpredictable for now.
|
||||
uint opcode = 0xe7c00010u; // BFI R0, R0, #0, #1
|
||||
@ -59,9 +57,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 0xdu)] uint rn,
|
||||
[Random(RndCnt)] uint wd,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint lsb,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint widthm1)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0u, 15u, 16u, 31u)] uint lsb,
|
||||
[Values(0u, 15u, 16u, 31u)] uint widthm1)
|
||||
{
|
||||
if (lsb + widthm1 > 31)
|
||||
{
|
||||
@ -84,9 +82,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 0xdu)] uint rn,
|
||||
[Random(RndCnt)] uint wd,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint lsb,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint widthm1)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0u, 15u, 16u, 31u)] uint lsb,
|
||||
[Values(0u, 15u, 16u, 31u)] uint widthm1)
|
||||
{
|
||||
if (lsb + widthm1 > 31)
|
||||
{
|
||||
@ -105,4 +103,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -9,17 +9,15 @@ namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
#if Bfm
|
||||
private const int RndCnt = 2;
|
||||
private const int RndCntImmr = 2;
|
||||
private const int RndCntImms = 2;
|
||||
|
||||
[Test, Pairwise, Description("BFM <Xd>, <Xn>, #<immr>, #<imms>")]
|
||||
public void Bfm_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Random(RndCnt)] ulong xd,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr,
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms)
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0u, 31u, 32u, 63u)] uint immr,
|
||||
[Values(0u, 31u, 32u, 63u)] uint imms)
|
||||
{
|
||||
uint opcode = 0xB3400000; // BFM X0, X0, #0, #0
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -37,9 +35,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Random(RndCnt)] uint wd,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0u, 15u, 16u, 31u)] uint immr,
|
||||
[Values(0u, 15u, 16u, 31u)] uint imms)
|
||||
{
|
||||
uint opcode = 0x33000000; // BFM W0, W0, #0, #0
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -56,9 +54,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Sbfm_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr,
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms)
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0u, 31u, 32u, 63u)] uint immr,
|
||||
[Values(0u, 31u, 32u, 63u)] uint imms)
|
||||
{
|
||||
uint opcode = 0x93400000; // SBFM X0, X0, #0, #0
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -75,9 +73,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Sbfm_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0u, 15u, 16u, 31u)] uint immr,
|
||||
[Values(0u, 15u, 16u, 31u)] uint imms)
|
||||
{
|
||||
uint opcode = 0x13000000; // SBFM W0, W0, #0, #0
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -94,9 +92,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Ubfm_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr,
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms)
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0u, 31u, 32u, 63u)] uint immr,
|
||||
[Values(0u, 31u, 32u, 63u)] uint imms)
|
||||
{
|
||||
uint opcode = 0xD3400000; // UBFM X0, X0, #0, #0
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -113,9 +111,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Ubfm_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr,
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0u, 15u, 16u, 31u)] uint immr,
|
||||
[Values(0u, 15u, 16u, 31u)] uint imms)
|
||||
{
|
||||
uint opcode = 0x53000000; // UBFM W0, W0, #0, #0
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -129,4 +127,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -8,15 +8,13 @@ namespace Ryujinx.Tests.Cpu
|
||||
public sealed class CpuTestCcmpImm : CpuTest
|
||||
{
|
||||
#if CcmpImm
|
||||
private const int RndCnt = 2;
|
||||
private const int RndCntImm = 2;
|
||||
private const int RndCntNzcv = 2;
|
||||
|
||||
[Test, Pairwise, Description("CCMN <Xn>, #<imm>, #<nzcv>, <cond>")]
|
||||
public void Ccmn_64bit([Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
[Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0u, 31u)] uint imm,
|
||||
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
@ -37,8 +35,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("CCMN <Wn>, #<imm>, #<nzcv>, <cond>")]
|
||||
public void Ccmn_32bit([Values(1u, 31u)] uint rn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0u, 31u)] uint imm,
|
||||
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
@ -59,8 +57,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("CCMP <Xn>, #<imm>, #<nzcv>, <cond>")]
|
||||
public void Ccmp_64bit([Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
[Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0u, 31u)] uint imm,
|
||||
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
@ -81,8 +79,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("CCMP <Wn>, #<imm>, #<nzcv>, <cond>")]
|
||||
public void Ccmp_32bit([Values(1u, 31u)] uint rn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0u, 31u)] uint imm,
|
||||
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
@ -101,4 +99,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -8,16 +8,15 @@ namespace Ryujinx.Tests.Cpu
|
||||
public sealed class CpuTestCcmpReg : CpuTest
|
||||
{
|
||||
#if CcmpReg
|
||||
private const int RndCnt = 2;
|
||||
private const int RndCntNzcv = 2;
|
||||
|
||||
[Test, Pairwise, Description("CCMN <Xn>, <Xm>, #<nzcv>, <cond>")]
|
||||
public void Ccmn_64bit([Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
@ -39,9 +38,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Ccmn_32bit([Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
@ -63,9 +62,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Ccmp_64bit([Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
@ -87,9 +86,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Ccmp_32bit([Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
@ -108,4 +107,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -8,16 +8,15 @@ namespace Ryujinx.Tests.Cpu
|
||||
public sealed class CpuTestCsel : CpuTest
|
||||
{
|
||||
#if Csel
|
||||
private const int RndCnt = 2;
|
||||
|
||||
[Test, Pairwise, Description("CSEL <Xd>, <Xn>, <Xm>, <cond>")]
|
||||
public void Csel_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
|
||||
@ -39,9 +38,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
|
||||
@ -63,9 +62,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
|
||||
@ -87,9 +86,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
|
||||
@ -111,9 +110,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
|
||||
@ -135,9 +134,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
|
||||
@ -159,9 +158,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
|
||||
@ -183,9 +182,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
|
||||
@ -203,4 +202,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,9 +1,7 @@
|
||||
#define Misc
|
||||
|
||||
using ARMeilleure.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
using System;
|
||||
using System.Collections.Generic;
|
||||
|
||||
@ -59,7 +57,6 @@ namespace Ryujinx.Tests.Cpu
|
||||
#endregion
|
||||
|
||||
private const int RndCnt = 2;
|
||||
private const int RndCntImm = 2;
|
||||
|
||||
private static readonly bool NoZeros = false;
|
||||
private static readonly bool NoInfs = false;
|
||||
@ -68,8 +65,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "AluImm & Csel"
|
||||
[Test, Pairwise]
|
||||
public void Adds_Csinc_64bit([Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0u, 4095u)] uint imm,
|
||||
[Values(0b00u, 0b01u)] uint shift, // <LSL #0, LSL #12>
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
@ -93,8 +90,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Adds_Csinc_32bit([Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0u, 4095u)] uint imm,
|
||||
[Values(0b00u, 0b01u)] uint shift, // <LSL #0, LSL #12>
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
@ -118,8 +115,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Subs_Csinc_64bit([Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0u, 4095u)] uint imm,
|
||||
[Values(0b00u, 0b01u)] uint shift, // <LSL #0, LSL #12>
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
@ -143,8 +140,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Subs_Csinc_32bit([Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0u, 4095u)] uint imm,
|
||||
[Values(0b00u, 0b01u)] uint shift, // <LSL #0, LSL #12>
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
@ -412,9 +409,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
[Explicit]
|
||||
[Test, Pairwise]
|
||||
public void Misc4([ValueSource("_1S_F_")] ulong a,
|
||||
[ValueSource("_1S_F_")] ulong b,
|
||||
[ValueSource("_1S_F_")] ulong c,
|
||||
public void Misc4([ValueSource(nameof(_1S_F_))] ulong a,
|
||||
[ValueSource(nameof(_1S_F_))] ulong b,
|
||||
[ValueSource(nameof(_1S_F_))] ulong c,
|
||||
[Values(0ul, 1ul, 2ul, 3ul)] ulong displacement)
|
||||
{
|
||||
if (!BitConverter.IsLittleEndian)
|
||||
@ -460,7 +457,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
[Explicit]
|
||||
[Test]
|
||||
public void Misc5([ValueSource("_1S_F_")] ulong a)
|
||||
public void Misc5([ValueSource(nameof(_1S_F_))] ulong a)
|
||||
{
|
||||
SetContext(
|
||||
v0: MakeVectorE0E1(a, TestContext.CurrentContext.Random.NextULong()),
|
||||
@ -482,4 +479,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,9 +1,7 @@
|
||||
#define Misc32
|
||||
|
||||
using ARMeilleure.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
using System.Collections.Generic;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
@ -64,8 +62,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
private static readonly bool NoNaNs = false;
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Vmsr_Vcmp_Vmrs([ValueSource("_1S_F_")] ulong a,
|
||||
[ValueSource("_1S_F_")] ulong b,
|
||||
public void Vmsr_Vcmp_Vmrs([ValueSource(nameof(_1S_F_))] ulong a,
|
||||
[ValueSource(nameof(_1S_F_))] ulong b,
|
||||
[Values] bool mode1,
|
||||
[Values] bool mode2,
|
||||
[Values] bool mode3)
|
||||
|
||||
@ -9,12 +9,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
#if Mov
|
||||
private const int RndCnt = 2;
|
||||
private const int RndCntImm = 2;
|
||||
|
||||
[Test, Pairwise, Description("MOVK <Xd>, #<imm>{, LSL #<shift>}")]
|
||||
public void Movk_64bit([Values(0u, 31u)] uint rd,
|
||||
[Random(RndCnt)] ulong xd,
|
||||
[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
|
||||
[Values(0u, 65535u)] uint imm,
|
||||
[Values(0u, 16u, 32u, 48u)] uint shift)
|
||||
{
|
||||
uint opcode = 0xF2800000; // MOVK X0, #0, LSL #0
|
||||
@ -31,7 +30,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("MOVK <Wd>, #<imm>{, LSL #<shift>}")]
|
||||
public void Movk_32bit([Values(0u, 31u)] uint rd,
|
||||
[Random(RndCnt)] uint wd,
|
||||
[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
|
||||
[Values(0u, 65535u)] uint imm,
|
||||
[Values(0u, 16u)] uint shift)
|
||||
{
|
||||
uint opcode = 0x72800000; // MOVK W0, #0, LSL #0
|
||||
@ -47,7 +46,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
[Test, Pairwise, Description("MOVN <Xd>, #<imm>{, LSL #<shift>}")]
|
||||
public void Movn_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
|
||||
[Values(0u, 65535u)] uint imm,
|
||||
[Values(0u, 16u, 32u, 48u)] uint shift)
|
||||
{
|
||||
uint opcode = 0x92800000; // MOVN X0, #0, LSL #0
|
||||
@ -63,7 +62,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
[Test, Pairwise, Description("MOVN <Wd>, #<imm>{, LSL #<shift>}")]
|
||||
public void Movn_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
|
||||
[Values(0u, 65535u)] uint imm,
|
||||
[Values(0u, 16u)] uint shift)
|
||||
{
|
||||
uint opcode = 0x12800000; // MOVN W0, #0, LSL #0
|
||||
@ -79,7 +78,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
[Test, Pairwise, Description("MOVZ <Xd>, #<imm>{, LSL #<shift>}")]
|
||||
public void Movz_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
|
||||
[Values(0u, 65535u)] uint imm,
|
||||
[Values(0u, 16u, 32u, 48u)] uint shift)
|
||||
{
|
||||
uint opcode = 0xD2800000; // MOVZ X0, #0, LSL #0
|
||||
@ -95,7 +94,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
[Test, Pairwise, Description("MOVZ <Wd>, #<imm>{, LSL #<shift>}")]
|
||||
public void Movz_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
|
||||
[Values(0u, 65535u)] uint imm,
|
||||
[Values(0u, 16u)] uint shift)
|
||||
{
|
||||
uint opcode = 0x52800000; // MOVZ W0, #0, LSL #0
|
||||
@ -110,4 +109,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -8,19 +8,17 @@ namespace Ryujinx.Tests.Cpu
|
||||
public sealed class CpuTestMul : CpuTest
|
||||
{
|
||||
#if Mul
|
||||
private const int RndCnt = 2;
|
||||
|
||||
[Test, Pairwise, Description("MADD <Xd>, <Xn>, <Xm>, <Xa>")]
|
||||
public void Madd_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(3u, 31u)] uint ra,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xa)
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xa)
|
||||
{
|
||||
uint opcode = 0x9B000000; // MADD X0, X0, X0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((ra & 31) << 10) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -38,11 +36,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(3u, 31u)] uint ra,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wa)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wa)
|
||||
{
|
||||
uint opcode = 0x1B000000; // MADD W0, W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((ra & 31) << 10) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -60,11 +58,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(3u, 31u)] uint ra,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xa)
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xa)
|
||||
{
|
||||
uint opcode = 0x9B008000; // MSUB X0, X0, X0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((ra & 31) << 10) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -82,11 +80,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(3u, 31u)] uint ra,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wa)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wa)
|
||||
{
|
||||
uint opcode = 0x1B008000; // MSUB W0, W0, W0, W0
|
||||
opcode |= ((rm & 31) << 16) | ((ra & 31) << 10) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -104,11 +102,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(3u, 31u)] uint ra,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xa)
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xa)
|
||||
{
|
||||
uint opcode = 0x9B200000; // SMADDL X0, W0, W0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((ra & 31) << 10) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -126,11 +124,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(3u, 31u)] uint ra,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xa)
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xa)
|
||||
{
|
||||
uint opcode = 0x9BA00000; // UMADDL X0, W0, W0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((ra & 31) << 10) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -148,11 +146,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(3u, 31u)] uint ra,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xa)
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xa)
|
||||
{
|
||||
uint opcode = 0x9B208000; // SMSUBL X0, W0, W0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((ra & 31) << 10) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -170,11 +168,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(3u, 31u)] uint ra,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xa)
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xa)
|
||||
{
|
||||
uint opcode = 0x9BA08000; // UMSUBL X0, W0, W0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((ra & 31) << 10) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -191,9 +189,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm)
|
||||
{
|
||||
uint opcode = 0x9B407C00; // SMULH X0, X0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -210,9 +208,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(2u, 31u)] uint rm,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm)
|
||||
{
|
||||
uint opcode = 0x9BC07C00; // UMULH X0, X0, X0
|
||||
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -225,4 +223,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -12,7 +12,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Opcodes)"
|
||||
private static uint[] _Smlabb_Smlabt_Smlatb_Smlatt_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xe1000080u, // SMLABB R0, R0, R0, R0
|
||||
0xe10000C0u, // SMLABT R0, R0, R0, R0
|
||||
@ -23,7 +23,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Smlawb_Smlawt_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xe1200080u, // SMLAWB R0, R0, R0, R0
|
||||
0xe12000C0u, // SMLAWT R0, R0, R0, R0
|
||||
@ -32,7 +32,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Smulbb_Smulbt_Smultb_Smultt_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xe1600080u, // SMULBB R0, R0, R0
|
||||
0xe16000C0u, // SMULBT R0, R0, R0
|
||||
@ -43,7 +43,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Smulwb_Smulwt_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xe12000a0u, // SMULWB R0, R0, R0
|
||||
0xe12000e0u, // SMULWT R0, R0, R0
|
||||
@ -51,8 +51,6 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endregion
|
||||
|
||||
private const int RndCnt = 2;
|
||||
|
||||
[Test, Pairwise, Description("SMLA<x><y> <Rd>, <Rn>, <Rm>, <Ra>")]
|
||||
public void Smla___32bit([ValueSource("_Smlabb_Smlabt_Smlatb_Smlatt_")] uint opcode,
|
||||
[Values(0u, 0xdu)] uint rn,
|
||||
@ -60,11 +58,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(2u, 0xdu)] uint ra,
|
||||
[Values(3u, 0xdu)] uint rd,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wa)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wa)
|
||||
{
|
||||
opcode |= ((rn & 15) << 0) | ((rm & 15) << 8) | ((ra & 15) << 12) | ((rd & 15) << 16);
|
||||
|
||||
@ -82,11 +80,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(2u, 0xdu)] uint ra,
|
||||
[Values(3u, 0xdu)] uint rd,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wa)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wa)
|
||||
{
|
||||
opcode |= ((rn & 15) << 0) | ((rm & 15) << 8) | ((ra & 15) << 12) | ((rd & 15) << 16);
|
||||
|
||||
@ -103,9 +101,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 0xdu)] uint rm,
|
||||
[Values(2u, 0xdu)] uint rd,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm)
|
||||
{
|
||||
opcode |= ((rn & 15) << 0) | ((rm & 15) << 8) | ((rd & 15) << 16);
|
||||
|
||||
@ -122,9 +120,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 0xdu)] uint rm,
|
||||
[Values(2u, 0xdu)] uint rd,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wm)
|
||||
{
|
||||
opcode |= ((rn & 15) << 0) | ((rm & 15) << 8) | ((rd & 15) << 16);
|
||||
|
||||
@ -136,4 +134,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -14,7 +14,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Opcodes)"
|
||||
private static uint[] _Vabs_Vneg_Vpaddl_I_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xf3b10300u, // VABS.S8 D0, D0
|
||||
0xf3b10380u, // VNEG.S8 D0, D0
|
||||
@ -24,7 +24,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Vabs_Vneg_F_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xf3b90700u, // VABS.F32 D0, D0
|
||||
0xf3b90780u // VNEG.F32 D0, D0
|
||||
@ -35,10 +35,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Types)"
|
||||
private static ulong[] _8B4H2S_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static IEnumerable<ulong> _1S_F_()
|
||||
@ -211,11 +211,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Vabs_Vneg_Vpaddl_V_I([ValueSource("_Vabs_Vneg_Vpaddl_I_")] uint opcode,
|
||||
public void Vabs_Vneg_Vpaddl_V_I([ValueSource(nameof(_Vabs_Vneg_Vpaddl_I_))] uint opcode,
|
||||
[Range(0u, 3u)] uint rd,
|
||||
[Range(0u, 3u)] uint rm,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong b,
|
||||
[ValueSource(nameof(_8B4H2S_))] ulong z,
|
||||
[ValueSource(nameof(_8B4H2S_))] ulong b,
|
||||
[Values(0u, 1u, 2u)] uint size, // <S8, S16, S32>
|
||||
[Values] bool q)
|
||||
{
|
||||
@ -241,11 +241,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Vabs_Vneg_V_F32([ValueSource("_Vabs_Vneg_F_")] uint opcode,
|
||||
public void Vabs_Vneg_V_F32([ValueSource(nameof(_Vabs_Vneg_F_))] uint opcode,
|
||||
[Range(0u, 3u)] uint rd,
|
||||
[Range(0u, 3u)] uint rm,
|
||||
[ValueSource("_2S_F_")] ulong z,
|
||||
[ValueSource("_2S_F_")] ulong b,
|
||||
[ValueSource(nameof(_2S_F_))] ulong z,
|
||||
[ValueSource(nameof(_2S_F_))] ulong b,
|
||||
[Values] bool q)
|
||||
{
|
||||
if (q)
|
||||
@ -270,7 +270,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("VCNT.8 D0, D0 | VCNT.8 Q0, Q0")]
|
||||
public void Vcnt([Values(0u, 1u)] uint rd,
|
||||
[Values(0u, 1u)] uint rm,
|
||||
[ValueSource(nameof(_GenPopCnt8B_))] [Random(RndCnt)] ulong d0,
|
||||
[ValueSource(nameof(_GenPopCnt8B_))] ulong d0,
|
||||
[Values] bool q)
|
||||
{
|
||||
ulong d1 = ~d0; // It's expensive to have a second generator.
|
||||
@ -298,8 +298,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise]
|
||||
public void Vmovn_V([Range(0u, 3u)] uint rd,
|
||||
[Range(0u, 3u)] uint rm,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong b,
|
||||
[ValueSource(nameof(_8B4H2S_))] ulong z,
|
||||
[ValueSource(nameof(_8B4H2S_))] ulong b,
|
||||
[Values(0u, 1u, 2u, 3u)] uint op,
|
||||
[Values(0u, 1u, 2u)] uint size) // <S8, S16, S32>
|
||||
{
|
||||
@ -322,4 +322,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,9 +1,7 @@
|
||||
#define SimdCvt
|
||||
|
||||
using ARMeilleure.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
using System;
|
||||
using System.Collections.Generic;
|
||||
|
||||
@ -17,14 +15,14 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Types)"
|
||||
private static uint[] _W_()
|
||||
{
|
||||
return new uint[] { 0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu };
|
||||
return new[] { 0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu };
|
||||
}
|
||||
|
||||
private static ulong[] _X_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static IEnumerable<ulong> _1S_F_WX_()
|
||||
@ -89,13 +87,13 @@ namespace Ryujinx.Tests.Cpu
|
||||
ulong grbg = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
ulong rnd1 = (uint)BitConverter.SingleToInt32Bits(
|
||||
(float)((int)TestContext.CurrentContext.Random.NextUInt()));
|
||||
(int)TestContext.CurrentContext.Random.NextUInt());
|
||||
ulong rnd2 = (uint)BitConverter.SingleToInt32Bits(
|
||||
(float)((long)TestContext.CurrentContext.Random.NextULong()));
|
||||
(long)TestContext.CurrentContext.Random.NextULong());
|
||||
ulong rnd3 = (uint)BitConverter.SingleToInt32Bits(
|
||||
(float)((uint)TestContext.CurrentContext.Random.NextUInt()));
|
||||
TestContext.CurrentContext.Random.NextUInt());
|
||||
ulong rnd4 = (uint)BitConverter.SingleToInt32Bits(
|
||||
(float)((ulong)TestContext.CurrentContext.Random.NextULong()));
|
||||
TestContext.CurrentContext.Random.NextULong());
|
||||
|
||||
ulong rnd5 = GenNormalS();
|
||||
ulong rnd6 = GenSubnormalS();
|
||||
@ -170,13 +168,13 @@ namespace Ryujinx.Tests.Cpu
|
||||
for (int cnt = 1; cnt <= RndCnt; cnt++)
|
||||
{
|
||||
ulong rnd1 = (ulong)BitConverter.DoubleToInt64Bits(
|
||||
(double)((int)TestContext.CurrentContext.Random.NextUInt()));
|
||||
(int)TestContext.CurrentContext.Random.NextUInt());
|
||||
ulong rnd2 = (ulong)BitConverter.DoubleToInt64Bits(
|
||||
(double)((long)TestContext.CurrentContext.Random.NextULong()));
|
||||
(long)TestContext.CurrentContext.Random.NextULong());
|
||||
ulong rnd3 = (ulong)BitConverter.DoubleToInt64Bits(
|
||||
(double)((uint)TestContext.CurrentContext.Random.NextUInt()));
|
||||
TestContext.CurrentContext.Random.NextUInt());
|
||||
ulong rnd4 = (ulong)BitConverter.DoubleToInt64Bits(
|
||||
(double)((ulong)TestContext.CurrentContext.Random.NextULong()));
|
||||
TestContext.CurrentContext.Random.NextULong());
|
||||
|
||||
ulong rnd5 = GenNormalD();
|
||||
ulong rnd6 = GenSubnormalD();
|
||||
@ -195,7 +193,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Opcodes)"
|
||||
private static uint[] _F_Cvt_AMPZ_SU_Gp_SW_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x1E240000u, // FCVTAS W0, S0
|
||||
0x1E250000u, // FCVTAU W0, S0
|
||||
@ -211,7 +209,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _F_Cvt_AMPZ_SU_Gp_SX_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x9E240000u, // FCVTAS X0, S0
|
||||
0x9E250000u, // FCVTAU X0, S0
|
||||
@ -227,7 +225,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _F_Cvt_AMPZ_SU_Gp_DW_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x1E640000u, // FCVTAS W0, D0
|
||||
0x1E650000u, // FCVTAU W0, D0
|
||||
@ -243,7 +241,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _F_Cvt_AMPZ_SU_Gp_DX_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x9E640000u, // FCVTAS X0, D0
|
||||
0x9E650000u, // FCVTAU X0, D0
|
||||
@ -259,7 +257,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _F_Cvt_Z_SU_Gp_Fixed_SW_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x1E188000u, // FCVTZS W0, S0, #32
|
||||
0x1E198000u // FCVTZU W0, S0, #32
|
||||
@ -268,7 +266,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _F_Cvt_Z_SU_Gp_Fixed_SX_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x9E180000u, // FCVTZS X0, S0, #64
|
||||
0x9E190000u // FCVTZU X0, S0, #64
|
||||
@ -277,7 +275,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _F_Cvt_Z_SU_Gp_Fixed_DW_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x1E588000u, // FCVTZS W0, D0, #32
|
||||
0x1E598000u // FCVTZU W0, D0, #32
|
||||
@ -286,7 +284,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _F_Cvt_Z_SU_Gp_Fixed_DX_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x9E580000u, // FCVTZS X0, D0, #64
|
||||
0x9E590000u // FCVTZU X0, D0, #64
|
||||
@ -295,7 +293,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _SU_Cvt_F_Gp_WS_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x1E220000u, // SCVTF S0, W0
|
||||
0x1E230000u // UCVTF S0, W0
|
||||
@ -304,7 +302,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _SU_Cvt_F_Gp_WD_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x1E620000u, // SCVTF D0, W0
|
||||
0x1E630000u // UCVTF D0, W0
|
||||
@ -313,7 +311,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _SU_Cvt_F_Gp_XS_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x9E220000u, // SCVTF S0, X0
|
||||
0x9E230000u // UCVTF S0, X0
|
||||
@ -322,7 +320,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _SU_Cvt_F_Gp_XD_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x9E620000u, // SCVTF D0, X0
|
||||
0x9E630000u // UCVTF D0, X0
|
||||
@ -331,7 +329,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _SU_Cvt_F_Gp_Fixed_WS_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x1E028000u, // SCVTF S0, W0, #32
|
||||
0x1E038000u // UCVTF S0, W0, #32
|
||||
@ -340,7 +338,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _SU_Cvt_F_Gp_Fixed_WD_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x1E428000u, // SCVTF D0, W0, #32
|
||||
0x1E438000u // UCVTF D0, W0, #32
|
||||
@ -349,7 +347,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _SU_Cvt_F_Gp_Fixed_XS_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x9E020000u, // SCVTF S0, X0, #64
|
||||
0x9E030000u // UCVTF S0, X0, #64
|
||||
@ -358,7 +356,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _SU_Cvt_F_Gp_Fixed_XD_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x9E420000u, // SCVTF D0, X0, #64
|
||||
0x9E430000u // UCVTF D0, X0, #64
|
||||
@ -367,17 +365,16 @@ namespace Ryujinx.Tests.Cpu
|
||||
#endregion
|
||||
|
||||
private const int RndCnt = 2;
|
||||
private const int RndCntFBits = 2;
|
||||
|
||||
private static readonly bool NoZeros = false;
|
||||
private static readonly bool NoInfs = false;
|
||||
private static readonly bool NoNaNs = false;
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Cvt_AMPZ_SU_Gp_SW([ValueSource("_F_Cvt_AMPZ_SU_Gp_SW_")] uint opcodes,
|
||||
public void F_Cvt_AMPZ_SU_Gp_SW([ValueSource(nameof(_F_Cvt_AMPZ_SU_Gp_SW_))] uint opcodes,
|
||||
[Values(0u, 31u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[ValueSource("_1S_F_WX_")] ulong a)
|
||||
[ValueSource(nameof(_1S_F_WX_))] ulong a)
|
||||
{
|
||||
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
@ -391,10 +388,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Cvt_AMPZ_SU_Gp_SX([ValueSource("_F_Cvt_AMPZ_SU_Gp_SX_")] uint opcodes,
|
||||
public void F_Cvt_AMPZ_SU_Gp_SX([ValueSource(nameof(_F_Cvt_AMPZ_SU_Gp_SX_))] uint opcodes,
|
||||
[Values(0u, 31u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[ValueSource("_1S_F_WX_")] ulong a)
|
||||
[ValueSource(nameof(_1S_F_WX_))] ulong a)
|
||||
{
|
||||
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
@ -407,10 +404,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Cvt_AMPZ_SU_Gp_DW([ValueSource("_F_Cvt_AMPZ_SU_Gp_DW_")] uint opcodes,
|
||||
public void F_Cvt_AMPZ_SU_Gp_DW([ValueSource(nameof(_F_Cvt_AMPZ_SU_Gp_DW_))] uint opcodes,
|
||||
[Values(0u, 31u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[ValueSource("_1D_F_WX_")] ulong a)
|
||||
[ValueSource(nameof(_1D_F_WX_))] ulong a)
|
||||
{
|
||||
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
@ -424,10 +421,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Cvt_AMPZ_SU_Gp_DX([ValueSource("_F_Cvt_AMPZ_SU_Gp_DX_")] uint opcodes,
|
||||
public void F_Cvt_AMPZ_SU_Gp_DX([ValueSource(nameof(_F_Cvt_AMPZ_SU_Gp_DX_))] uint opcodes,
|
||||
[Values(0u, 31u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[ValueSource("_1D_F_WX_")] ulong a)
|
||||
[ValueSource(nameof(_1D_F_WX_))] ulong a)
|
||||
{
|
||||
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
@ -440,11 +437,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Cvt_Z_SU_Gp_Fixed_SW([ValueSource("_F_Cvt_Z_SU_Gp_Fixed_SW_")] uint opcodes,
|
||||
public void F_Cvt_Z_SU_Gp_Fixed_SW([ValueSource(nameof(_F_Cvt_Z_SU_Gp_Fixed_SW_))] uint opcodes,
|
||||
[Values(0u, 31u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[ValueSource("_1S_F_WX_")] ulong a,
|
||||
[Values(1u, 32u)] [Random(2u, 31u, RndCntFBits)] uint fBits)
|
||||
[ValueSource(nameof(_1S_F_WX_))] ulong a,
|
||||
[Values(1u, 32u)] uint fBits)
|
||||
{
|
||||
uint scale = (64u - fBits) & 0x3Fu;
|
||||
|
||||
@ -461,11 +458,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Cvt_Z_SU_Gp_Fixed_SX([ValueSource("_F_Cvt_Z_SU_Gp_Fixed_SX_")] uint opcodes,
|
||||
public void F_Cvt_Z_SU_Gp_Fixed_SX([ValueSource(nameof(_F_Cvt_Z_SU_Gp_Fixed_SX_))] uint opcodes,
|
||||
[Values(0u, 31u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[ValueSource("_1S_F_WX_")] ulong a,
|
||||
[Values(1u, 64u)] [Random(2u, 63u, RndCntFBits)] uint fBits)
|
||||
[ValueSource(nameof(_1S_F_WX_))] ulong a,
|
||||
[Values(1u, 64u)] uint fBits)
|
||||
{
|
||||
uint scale = (64u - fBits) & 0x3Fu;
|
||||
|
||||
@ -481,11 +478,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Cvt_Z_SU_Gp_Fixed_DW([ValueSource("_F_Cvt_Z_SU_Gp_Fixed_DW_")] uint opcodes,
|
||||
public void F_Cvt_Z_SU_Gp_Fixed_DW([ValueSource(nameof(_F_Cvt_Z_SU_Gp_Fixed_DW_))] uint opcodes,
|
||||
[Values(0u, 31u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[ValueSource("_1D_F_WX_")] ulong a,
|
||||
[Values(1u, 32u)] [Random(2u, 31u, RndCntFBits)] uint fBits)
|
||||
[ValueSource(nameof(_1D_F_WX_))] ulong a,
|
||||
[Values(1u, 32u)] uint fBits)
|
||||
{
|
||||
uint scale = (64u - fBits) & 0x3Fu;
|
||||
|
||||
@ -502,11 +499,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Cvt_Z_SU_Gp_Fixed_DX([ValueSource("_F_Cvt_Z_SU_Gp_Fixed_DX_")] uint opcodes,
|
||||
public void F_Cvt_Z_SU_Gp_Fixed_DX([ValueSource(nameof(_F_Cvt_Z_SU_Gp_Fixed_DX_))] uint opcodes,
|
||||
[Values(0u, 31u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[ValueSource("_1D_F_WX_")] ulong a,
|
||||
[Values(1u, 64u)] [Random(2u, 63u, RndCntFBits)] uint fBits)
|
||||
[ValueSource(nameof(_1D_F_WX_))] ulong a,
|
||||
[Values(1u, 64u)] uint fBits)
|
||||
{
|
||||
uint scale = (64u - fBits) & 0x3Fu;
|
||||
|
||||
@ -522,10 +519,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void SU_Cvt_F_Gp_WS([ValueSource("_SU_Cvt_F_Gp_WS_")] uint opcodes,
|
||||
public void SU_Cvt_F_Gp_WS([ValueSource(nameof(_SU_Cvt_F_Gp_WS_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[ValueSource("_W_")] [Random(RndCnt)] uint wn)
|
||||
[ValueSource(nameof(_W_))] uint wn)
|
||||
{
|
||||
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
@ -539,10 +536,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void SU_Cvt_F_Gp_WD([ValueSource("_SU_Cvt_F_Gp_WD_")] uint opcodes,
|
||||
public void SU_Cvt_F_Gp_WD([ValueSource(nameof(_SU_Cvt_F_Gp_WD_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[ValueSource("_W_")] [Random(RndCnt)] uint wn)
|
||||
[ValueSource(nameof(_W_))] uint wn)
|
||||
{
|
||||
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
@ -556,10 +553,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void SU_Cvt_F_Gp_XS([ValueSource("_SU_Cvt_F_Gp_XS_")] uint opcodes,
|
||||
public void SU_Cvt_F_Gp_XS([ValueSource(nameof(_SU_Cvt_F_Gp_XS_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[ValueSource("_X_")] [Random(RndCnt)] ulong xn)
|
||||
[ValueSource(nameof(_X_))] ulong xn)
|
||||
{
|
||||
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
@ -573,10 +570,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void SU_Cvt_F_Gp_XD([ValueSource("_SU_Cvt_F_Gp_XD_")] uint opcodes,
|
||||
public void SU_Cvt_F_Gp_XD([ValueSource(nameof(_SU_Cvt_F_Gp_XD_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[ValueSource("_X_")] [Random(RndCnt)] ulong xn)
|
||||
[ValueSource(nameof(_X_))] ulong xn)
|
||||
{
|
||||
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
||||
@ -590,11 +587,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void SU_Cvt_F_Gp_Fixed_WS([ValueSource("_SU_Cvt_F_Gp_Fixed_WS_")] uint opcodes,
|
||||
public void SU_Cvt_F_Gp_Fixed_WS([ValueSource(nameof(_SU_Cvt_F_Gp_Fixed_WS_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[ValueSource("_W_")] [Random(RndCnt)] uint wn,
|
||||
[Values(1u, 32u)] [Random(2u, 31u, RndCntFBits)] uint fBits)
|
||||
[ValueSource(nameof(_W_))] uint wn,
|
||||
[Values(1u, 32u)] uint fBits)
|
||||
{
|
||||
uint scale = (64u - fBits) & 0x3Fu;
|
||||
|
||||
@ -611,11 +608,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void SU_Cvt_F_Gp_Fixed_WD([ValueSource("_SU_Cvt_F_Gp_Fixed_WD_")] uint opcodes,
|
||||
public void SU_Cvt_F_Gp_Fixed_WD([ValueSource(nameof(_SU_Cvt_F_Gp_Fixed_WD_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[ValueSource("_W_")] [Random(RndCnt)] uint wn,
|
||||
[Values(1u, 32u)] [Random(2u, 31u, RndCntFBits)] uint fBits)
|
||||
[ValueSource(nameof(_W_))] uint wn,
|
||||
[Values(1u, 32u)] uint fBits)
|
||||
{
|
||||
uint scale = (64u - fBits) & 0x3Fu;
|
||||
|
||||
@ -632,11 +629,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void SU_Cvt_F_Gp_Fixed_XS([ValueSource("_SU_Cvt_F_Gp_Fixed_XS_")] uint opcodes,
|
||||
public void SU_Cvt_F_Gp_Fixed_XS([ValueSource(nameof(_SU_Cvt_F_Gp_Fixed_XS_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[ValueSource("_X_")] [Random(RndCnt)] ulong xn,
|
||||
[Values(1u, 64u)] [Random(2u, 63u, RndCntFBits)] uint fBits)
|
||||
[ValueSource(nameof(_X_))] ulong xn,
|
||||
[Values(1u, 64u)] uint fBits)
|
||||
{
|
||||
uint scale = (64u - fBits) & 0x3Fu;
|
||||
|
||||
@ -653,11 +650,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void SU_Cvt_F_Gp_Fixed_XD([ValueSource("_SU_Cvt_F_Gp_Fixed_XD_")] uint opcodes,
|
||||
public void SU_Cvt_F_Gp_Fixed_XD([ValueSource(nameof(_SU_Cvt_F_Gp_Fixed_XD_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[ValueSource("_X_")] [Random(RndCnt)] ulong xn,
|
||||
[Values(1u, 64u)] [Random(2u, 63u, RndCntFBits)] uint fBits)
|
||||
[ValueSource(nameof(_X_))] ulong xn,
|
||||
[Values(1u, 64u)] uint fBits)
|
||||
{
|
||||
uint scale = (64u - fBits) & 0x3Fu;
|
||||
|
||||
@ -674,4 +671,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -15,7 +15,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Opcodes)"
|
||||
private static uint[] _Vrint_AMNP_V_F32_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xf3ba0500u, // VRINTA.F32 Q0, Q0
|
||||
0xf3ba0680u, // VRINTM.F32 Q0, Q0
|
||||
@ -28,8 +28,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Types)"
|
||||
private static uint[] _1S_()
|
||||
{
|
||||
return new uint[] { 0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu };
|
||||
return new[] { 0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu };
|
||||
}
|
||||
|
||||
private static IEnumerable<ulong> _1S_F_()
|
||||
@ -219,10 +219,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("VCVT.F32.<dt> <Sd>, <Sm>")]
|
||||
public void Vcvt_I32_F32([Values(0u, 1u, 2u, 3u)] uint rd,
|
||||
[Values(0u, 1u, 2u, 3u)] uint rm,
|
||||
[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s0,
|
||||
[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s1,
|
||||
[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s2,
|
||||
[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s3,
|
||||
[ValueSource(nameof(_1S_))] uint s0,
|
||||
[ValueSource(nameof(_1S_))] uint s1,
|
||||
[ValueSource(nameof(_1S_))] uint s2,
|
||||
[ValueSource(nameof(_1S_))] uint s3,
|
||||
[Values] bool unsigned, // <U32, S32>
|
||||
[Values(RMode.Rn)] RMode rMode)
|
||||
{
|
||||
@ -249,10 +249,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("VCVT.F64.<dt> <Dd>, <Sm>")]
|
||||
public void Vcvt_I32_F64([Values(0u, 1u)] uint rd,
|
||||
[Values(0u, 1u, 2u, 3u)] uint rm,
|
||||
[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s0,
|
||||
[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s1,
|
||||
[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s2,
|
||||
[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s3,
|
||||
[ValueSource(nameof(_1S_))] uint s0,
|
||||
[ValueSource(nameof(_1S_))] uint s1,
|
||||
[ValueSource(nameof(_1S_))] uint s2,
|
||||
[ValueSource(nameof(_1S_))] uint s3,
|
||||
[Values] bool unsigned, // <U32, S32>
|
||||
[Values(RMode.Rn)] RMode rMode)
|
||||
{
|
||||
@ -344,10 +344,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("VCVT<top>.F16.F32 <Sd>, <Dm>")]
|
||||
public void Vcvt_F32_F16([Values(0u, 1u, 2u, 3u)] uint rd,
|
||||
[Values(0u, 1u, 2u, 3u)] uint rm,
|
||||
[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s0,
|
||||
[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s1,
|
||||
[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s2,
|
||||
[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s3,
|
||||
[ValueSource(nameof(_1S_))] uint s0,
|
||||
[ValueSource(nameof(_1S_))] uint s1,
|
||||
[ValueSource(nameof(_1S_))] uint s2,
|
||||
[ValueSource(nameof(_1S_))] uint s3,
|
||||
[Values] bool top)
|
||||
{
|
||||
uint opcode = 0xeeb30a40; // VCVTB.F16.F32 S0, D0
|
||||
@ -428,4 +428,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,7 +1,6 @@
|
||||
#define SimdExt
|
||||
|
||||
using ARMeilleure.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
@ -14,22 +13,19 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource"
|
||||
private static ulong[] _8B_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
#endregion
|
||||
|
||||
private const int RndCnt = 2;
|
||||
private const int RndCntIndex = 2;
|
||||
|
||||
[Test, Pairwise, Description("EXT <Vd>.8B, <Vn>.8B, <Vm>.8B, #<index>")]
|
||||
public void Ext_V_8B([Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[Values(2u, 0u)] uint rm,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong b,
|
||||
[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index)
|
||||
[ValueSource(nameof(_8B_))] ulong z,
|
||||
[ValueSource(nameof(_8B_))] ulong a,
|
||||
[ValueSource(nameof(_8B_))] ulong b,
|
||||
[Values(0u, 7u)] uint index)
|
||||
{
|
||||
uint imm4 = index & 0x7u;
|
||||
|
||||
@ -50,10 +46,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Ext_V_16B([Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[Values(2u, 0u)] uint rm,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong b,
|
||||
[Values(0u, 15u)] [Random(1u, 14u, RndCntIndex)] uint index)
|
||||
[ValueSource(nameof(_8B_))] ulong z,
|
||||
[ValueSource(nameof(_8B_))] ulong a,
|
||||
[ValueSource(nameof(_8B_))] ulong b,
|
||||
[Values(0u, 15u)] uint index)
|
||||
{
|
||||
uint imm4 = index & 0xFu;
|
||||
|
||||
@ -71,4 +67,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,9 +1,7 @@
|
||||
#define SimdFcond
|
||||
|
||||
using ARMeilleure.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
using System.Collections.Generic;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
@ -101,7 +99,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Opcodes)"
|
||||
private static uint[] _F_Ccmp_Ccmpe_S_S_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x1E220420u, // FCCMP S1, S2, #0, EQ
|
||||
0x1E220430u // FCCMPE S1, S2, #0, EQ
|
||||
@ -110,7 +108,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _F_Ccmp_Ccmpe_S_D_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x1E620420u, // FCCMP D1, D2, #0, EQ
|
||||
0x1E620430u // FCCMPE D1, D2, #0, EQ
|
||||
@ -119,7 +117,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _F_Csel_S_S_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x1E220C20u // FCSEL S0, S1, S2, EQ
|
||||
};
|
||||
@ -127,7 +125,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _F_Csel_S_D_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x1E620C20u // FCSEL D0, D1, D2, EQ
|
||||
};
|
||||
@ -142,9 +140,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
private static readonly bool NoNaNs = false;
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Ccmp_Ccmpe_S_S([ValueSource("_F_Ccmp_Ccmpe_S_S_")] uint opcodes,
|
||||
[ValueSource("_1S_F_")] ulong a,
|
||||
[ValueSource("_1S_F_")] ulong b,
|
||||
public void F_Ccmp_Ccmpe_S_S([ValueSource(nameof(_F_Ccmp_Ccmpe_S_S_))] uint opcodes,
|
||||
[ValueSource(nameof(_1S_F_))] ulong a,
|
||||
[ValueSource(nameof(_1S_F_))] ulong b,
|
||||
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
@ -167,9 +165,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Ccmp_Ccmpe_S_D([ValueSource("_F_Ccmp_Ccmpe_S_D_")] uint opcodes,
|
||||
[ValueSource("_1D_F_")] ulong a,
|
||||
[ValueSource("_1D_F_")] ulong b,
|
||||
public void F_Ccmp_Ccmpe_S_D([ValueSource(nameof(_F_Ccmp_Ccmpe_S_D_))] uint opcodes,
|
||||
[ValueSource(nameof(_1D_F_))] ulong a,
|
||||
[ValueSource(nameof(_1D_F_))] ulong b,
|
||||
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
@ -192,9 +190,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Csel_S_S([ValueSource("_F_Csel_S_S_")] uint opcodes,
|
||||
[ValueSource("_1S_F_")] ulong a,
|
||||
[ValueSource("_1S_F_")] ulong b,
|
||||
public void F_Csel_S_S([ValueSource(nameof(_F_Csel_S_S_))] uint opcodes,
|
||||
[ValueSource(nameof(_1S_F_))] ulong a,
|
||||
[ValueSource(nameof(_1S_F_))] ulong b,
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
|
||||
@ -213,9 +211,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Csel_S_D([ValueSource("_F_Csel_S_D_")] uint opcodes,
|
||||
[ValueSource("_1D_F_")] ulong a,
|
||||
[ValueSource("_1D_F_")] ulong b,
|
||||
public void F_Csel_S_D([ValueSource(nameof(_F_Csel_S_D_))] uint opcodes,
|
||||
[ValueSource(nameof(_1D_F_))] ulong a,
|
||||
[ValueSource(nameof(_1D_F_))] ulong b,
|
||||
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
|
||||
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
|
||||
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
|
||||
|
||||
@ -1,7 +1,6 @@
|
||||
#define SimdFmov
|
||||
|
||||
using ARMeilleure.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
@ -14,7 +13,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource"
|
||||
private static uint[] _F_Mov_Si_S_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x1E201000u // FMOV S0, #2.0
|
||||
};
|
||||
@ -22,7 +21,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _F_Mov_Si_D_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x1E601000u // FMOV D0, #2.0
|
||||
};
|
||||
@ -30,7 +29,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
#endregion
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Mov_Si_S([ValueSource("_F_Mov_Si_S_")] uint opcodes,
|
||||
public void F_Mov_Si_S([ValueSource(nameof(_F_Mov_Si_S_))] uint opcodes,
|
||||
[Range(0u, 255u, 1u)] uint imm8)
|
||||
{
|
||||
opcodes |= ((imm8 & 0xFFu) << 13);
|
||||
@ -44,7 +43,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Mov_Si_D([ValueSource("_F_Mov_Si_D_")] uint opcodes,
|
||||
public void F_Mov_Si_D([ValueSource(nameof(_F_Mov_Si_D_))] uint opcodes,
|
||||
[Range(0u, 255u, 1u)] uint imm8)
|
||||
{
|
||||
opcodes |= ((imm8 & 0xFFu) << 13);
|
||||
|
||||
@ -1,9 +1,7 @@
|
||||
#define SimdImm
|
||||
|
||||
using ARMeilleure.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
using System.Collections.Generic;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
@ -50,14 +48,14 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Types)"
|
||||
private static ulong[] _2S_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _4H_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static IEnumerable<byte> _8BIT_IMM_()
|
||||
@ -94,7 +92,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Opcodes)"
|
||||
private static uint[] _Bic_Orr_Vi_16bit_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x2F009400u, // BIC V0.4H, #0
|
||||
0x0F009400u // ORR V0.4H, #0
|
||||
@ -103,7 +101,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Bic_Orr_Vi_32bit_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x2F001400u, // BIC V0.2S, #0
|
||||
0x0F001400u // ORR V0.2S, #0
|
||||
@ -112,7 +110,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _F_Mov_Vi_2S_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F00F400u // FMOV V0.2S, #2.0
|
||||
};
|
||||
@ -120,7 +118,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _F_Mov_Vi_4S_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x4F00F400u // FMOV V0.4S, #2.0
|
||||
};
|
||||
@ -128,7 +126,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _F_Mov_Vi_2D_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x6F00F400u // FMOV V0.2D, #2.0
|
||||
};
|
||||
@ -136,7 +134,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Movi_V_8bit_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F00E400u // MOVI V0.8B, #0
|
||||
};
|
||||
@ -144,7 +142,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Movi_Mvni_V_16bit_shifted_imm_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F008400u, // MOVI V0.4H, #0
|
||||
0x2F008400u // MVNI V0.4H, #0
|
||||
@ -153,7 +151,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Movi_Mvni_V_32bit_shifted_imm_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F000400u, // MOVI V0.2S, #0
|
||||
0x2F000400u // MVNI V0.2S, #0
|
||||
@ -162,7 +160,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Movi_Mvni_V_32bit_shifting_ones_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F00C400u, // MOVI V0.2S, #0, MSL #8
|
||||
0x2F00C400u // MVNI V0.2S, #0, MSL #8
|
||||
@ -171,7 +169,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Movi_V_64bit_scalar_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x2F00E400u // MOVI D0, #0
|
||||
};
|
||||
@ -179,21 +177,20 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Movi_V_64bit_vector_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x6F00E400u // MOVI V0.2D, #0
|
||||
};
|
||||
}
|
||||
#endregion
|
||||
|
||||
private const int RndCnt = 2;
|
||||
private const int RndCntImm8 = 2;
|
||||
private const int RndCntImm64 = 2;
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Bic_Orr_Vi_16bit([ValueSource("_Bic_Orr_Vi_16bit_")] uint opcodes,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_8BIT_IMM_")] byte imm8,
|
||||
public void Bic_Orr_Vi_16bit([ValueSource(nameof(_Bic_Orr_Vi_16bit_))] uint opcodes,
|
||||
[ValueSource(nameof(_4H_))] ulong z,
|
||||
[ValueSource(nameof(_8BIT_IMM_))] byte imm8,
|
||||
[Values(0b0u, 0b1u)] uint amount, // <0, 8>
|
||||
[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
|
||||
{
|
||||
@ -212,9 +209,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Bic_Orr_Vi_32bit([ValueSource("_Bic_Orr_Vi_32bit_")] uint opcodes,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_8BIT_IMM_")] byte imm8,
|
||||
public void Bic_Orr_Vi_32bit([ValueSource(nameof(_Bic_Orr_Vi_32bit_))] uint opcodes,
|
||||
[ValueSource(nameof(_2S_))] ulong z,
|
||||
[ValueSource(nameof(_8BIT_IMM_))] byte imm8,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint amount, // <0, 8, 16, 24>
|
||||
[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
|
||||
{
|
||||
@ -233,7 +230,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Mov_Vi_2S([ValueSource("_F_Mov_Vi_2S_")] uint opcodes,
|
||||
public void F_Mov_Vi_2S([ValueSource(nameof(_F_Mov_Vi_2S_))] uint opcodes,
|
||||
[Range(0u, 255u, 1u)] uint abcdefgh)
|
||||
{
|
||||
uint abc = (abcdefgh & 0xE0u) >> 5;
|
||||
@ -250,7 +247,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Mov_Vi_4S([ValueSource("_F_Mov_Vi_4S_")] uint opcodes,
|
||||
public void F_Mov_Vi_4S([ValueSource(nameof(_F_Mov_Vi_4S_))] uint opcodes,
|
||||
[Range(0u, 255u, 1u)] uint abcdefgh)
|
||||
{
|
||||
uint abc = (abcdefgh & 0xE0u) >> 5;
|
||||
@ -264,7 +261,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Mov_Vi_2D([ValueSource("_F_Mov_Vi_2D_")] uint opcodes,
|
||||
public void F_Mov_Vi_2D([ValueSource(nameof(_F_Mov_Vi_2D_))] uint opcodes,
|
||||
[Range(0u, 255u, 1u)] uint abcdefgh)
|
||||
{
|
||||
uint abc = (abcdefgh & 0xE0u) >> 5;
|
||||
@ -278,8 +275,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Movi_V_8bit([ValueSource("_Movi_V_8bit_")] uint opcodes,
|
||||
[ValueSource("_8BIT_IMM_")] byte imm8,
|
||||
public void Movi_V_8bit([ValueSource(nameof(_Movi_V_8bit_))] uint opcodes,
|
||||
[ValueSource(nameof(_8BIT_IMM_))] byte imm8,
|
||||
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
|
||||
{
|
||||
uint abc = (imm8 & 0xE0u) >> 5;
|
||||
@ -297,8 +294,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Movi_Mvni_V_16bit_shifted_imm([ValueSource("_Movi_Mvni_V_16bit_shifted_imm_")] uint opcodes,
|
||||
[ValueSource("_8BIT_IMM_")] byte imm8,
|
||||
public void Movi_Mvni_V_16bit_shifted_imm([ValueSource(nameof(_Movi_Mvni_V_16bit_shifted_imm_))] uint opcodes,
|
||||
[ValueSource(nameof(_8BIT_IMM_))] byte imm8,
|
||||
[Values(0b0u, 0b1u)] uint amount, // <0, 8>
|
||||
[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
|
||||
{
|
||||
@ -318,8 +315,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Movi_Mvni_V_32bit_shifted_imm([ValueSource("_Movi_Mvni_V_32bit_shifted_imm_")] uint opcodes,
|
||||
[ValueSource("_8BIT_IMM_")] byte imm8,
|
||||
public void Movi_Mvni_V_32bit_shifted_imm([ValueSource(nameof(_Movi_Mvni_V_32bit_shifted_imm_))] uint opcodes,
|
||||
[ValueSource(nameof(_8BIT_IMM_))] byte imm8,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint amount, // <0, 8, 16, 24>
|
||||
[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
|
||||
{
|
||||
@ -339,8 +336,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Movi_Mvni_V_32bit_shifting_ones([ValueSource("_Movi_Mvni_V_32bit_shifting_ones_")] uint opcodes,
|
||||
[ValueSource("_8BIT_IMM_")] byte imm8,
|
||||
public void Movi_Mvni_V_32bit_shifting_ones([ValueSource(nameof(_Movi_Mvni_V_32bit_shifting_ones_))] uint opcodes,
|
||||
[ValueSource(nameof(_8BIT_IMM_))] byte imm8,
|
||||
[Values(0b0u, 0b1u)] uint amount, // <8, 16>
|
||||
[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
|
||||
{
|
||||
@ -360,8 +357,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Movi_V_64bit_scalar([ValueSource("_Movi_V_64bit_scalar_")] uint opcodes,
|
||||
[ValueSource("_64BIT_IMM_")] ulong imm)
|
||||
public void Movi_V_64bit_scalar([ValueSource(nameof(_Movi_V_64bit_scalar_))] uint opcodes,
|
||||
[ValueSource(nameof(_64BIT_IMM_))] ulong imm)
|
||||
{
|
||||
byte imm8 = ShrinkImm64(imm);
|
||||
|
||||
@ -379,8 +376,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Movi_V_64bit_vector([ValueSource("_Movi_V_64bit_vector_")] uint opcodes,
|
||||
[ValueSource("_64BIT_IMM_")] ulong imm)
|
||||
public void Movi_V_64bit_vector([ValueSource(nameof(_Movi_V_64bit_vector_))] uint opcodes,
|
||||
[ValueSource(nameof(_64BIT_IMM_))] ulong imm)
|
||||
{
|
||||
byte imm8 = ShrinkImm64(imm);
|
||||
|
||||
@ -395,4 +392,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,7 +1,6 @@
|
||||
#define SimdIns
|
||||
|
||||
using ARMeilleure.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
@ -14,66 +13,63 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource"
|
||||
private static ulong[] _1D_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _2S_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _4H_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _8B_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _8B4H_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _8B4H2S_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static uint[] _W_()
|
||||
{
|
||||
return new uint[] { 0x00000000u, 0x0000007Fu,
|
||||
0x00000080u, 0x000000FFu,
|
||||
0x00007FFFu, 0x00008000u,
|
||||
0x0000FFFFu, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu };
|
||||
return new[] { 0x00000000u, 0x0000007Fu,
|
||||
0x00000080u, 0x000000FFu,
|
||||
0x00007FFFu, 0x00008000u,
|
||||
0x0000FFFFu, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu };
|
||||
}
|
||||
|
||||
private static ulong[] _X_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
#endregion
|
||||
|
||||
private const int RndCnt = 2;
|
||||
private const int RndCntIndex = 2;
|
||||
|
||||
[Test, Pairwise, Description("DUP <Vd>.<T>, W<n>")]
|
||||
public void Dup_Gp_W([Values(0u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[ValueSource("_W_")] [Random(RndCnt)] uint wn,
|
||||
[ValueSource(nameof(_W_))] uint wn,
|
||||
[Values(0, 1, 2)] int size, // Q0: <8B, 4H, 2S>
|
||||
[Values(0b0u, 0b1u)] uint q) // Q1: <16B, 8H, 4S>
|
||||
{
|
||||
@ -96,7 +92,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("DUP <Vd>.<T>, X<n>")]
|
||||
public void Dup_Gp_X([Values(0u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[ValueSource("_X_")] [Random(RndCnt)] ulong xn)
|
||||
[ValueSource(nameof(_X_))] ulong xn)
|
||||
{
|
||||
uint opcode = 0x4E080C00; // DUP V0.2D, X0
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -111,8 +107,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("DUP B0, V1.B[<index>]")]
|
||||
public void Dup_S_B([ValueSource("_8B_")] [Random(RndCnt)] ulong a,
|
||||
[Values(0u, 15u)] [Random(1u, 14u, RndCntIndex)] uint index)
|
||||
public void Dup_S_B([ValueSource(nameof(_8B_))] ulong a,
|
||||
[Values(0u, 15u)] uint index)
|
||||
{
|
||||
const int size = 0;
|
||||
|
||||
@ -131,8 +127,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("DUP H0, V1.H[<index>]")]
|
||||
public void Dup_S_H([ValueSource("_4H_")] [Random(RndCnt)] ulong a,
|
||||
[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index)
|
||||
public void Dup_S_H([ValueSource(nameof(_4H_))] ulong a,
|
||||
[Values(0u, 7u)] uint index)
|
||||
{
|
||||
const int size = 1;
|
||||
|
||||
@ -151,7 +147,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("DUP S0, V1.S[<index>]")]
|
||||
public void Dup_S_S([ValueSource("_2S_")] [Random(RndCnt)] ulong a,
|
||||
public void Dup_S_S([ValueSource(nameof(_2S_))] ulong a,
|
||||
[Values(0u, 1u, 2u, 3u)] uint index)
|
||||
{
|
||||
const int size = 2;
|
||||
@ -171,7 +167,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("DUP D0, V1.D[<index>]")]
|
||||
public void Dup_S_D([ValueSource("_1D_")] [Random(RndCnt)] ulong a,
|
||||
public void Dup_S_D([ValueSource(nameof(_1D_))] ulong a,
|
||||
[Values(0u, 1u)] uint index)
|
||||
{
|
||||
const int size = 3;
|
||||
@ -193,9 +189,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("DUP <Vd>.<T>, <Vn>.B[<index>]")]
|
||||
public void Dup_V_8B_16B([Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
|
||||
[Values(0u, 15u)] [Random(1u, 14u, RndCntIndex)] uint index,
|
||||
[ValueSource(nameof(_8B_))] ulong z,
|
||||
[ValueSource(nameof(_8B_))] ulong a,
|
||||
[Values(0u, 15u)] uint index,
|
||||
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
|
||||
{
|
||||
const int size = 0;
|
||||
@ -218,9 +214,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("DUP <Vd>.<T>, <Vn>.H[<index>]")]
|
||||
public void Dup_V_4H_8H([Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
|
||||
[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index,
|
||||
[ValueSource(nameof(_4H_))] ulong z,
|
||||
[ValueSource(nameof(_4H_))] ulong a,
|
||||
[Values(0u, 7u)] uint index,
|
||||
[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
|
||||
{
|
||||
const int size = 1;
|
||||
@ -243,8 +239,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("DUP <Vd>.<T>, <Vn>.S[<index>]")]
|
||||
public void Dup_V_2S_4S([Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
|
||||
[ValueSource(nameof(_2S_))] ulong z,
|
||||
[ValueSource(nameof(_2S_))] ulong a,
|
||||
[Values(0u, 1u, 2u, 3u)] uint index,
|
||||
[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
|
||||
{
|
||||
@ -268,8 +264,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("DUP <Vd>.<T>, <Vn>.D[<index>]")]
|
||||
public void Dup_V_2D([Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
|
||||
[ValueSource(nameof(_1D_))] ulong z,
|
||||
[ValueSource(nameof(_1D_))] ulong a,
|
||||
[Values(0u, 1u)] uint index,
|
||||
[Values(0b1u)] uint q) // <2D>
|
||||
{
|
||||
@ -293,9 +289,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("INS <Vd>.B[<index>], W<n>")]
|
||||
public void Ins_Gp_WB([Values(0u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_W_")] [Random(RndCnt)] uint wn,
|
||||
[Values(0u, 15u)] [Random(1u, 14u, RndCntIndex)] uint index)
|
||||
[ValueSource(nameof(_8B_))] ulong z,
|
||||
[ValueSource(nameof(_W_))] uint wn,
|
||||
[Values(0u, 15u)] uint index)
|
||||
{
|
||||
const int size = 0;
|
||||
|
||||
@ -316,9 +312,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("INS <Vd>.H[<index>], W<n>")]
|
||||
public void Ins_Gp_WH([Values(0u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_W_")] [Random(RndCnt)] uint wn,
|
||||
[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index)
|
||||
[ValueSource(nameof(_4H_))] ulong z,
|
||||
[ValueSource(nameof(_W_))] uint wn,
|
||||
[Values(0u, 7u)] uint index)
|
||||
{
|
||||
const int size = 1;
|
||||
|
||||
@ -339,8 +335,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("INS <Vd>.S[<index>], W<n>")]
|
||||
public void Ins_Gp_WS([Values(0u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_W_")] [Random(RndCnt)] uint wn,
|
||||
[ValueSource(nameof(_2S_))] ulong z,
|
||||
[ValueSource(nameof(_W_))] uint wn,
|
||||
[Values(0u, 1u, 2u, 3u)] uint index)
|
||||
{
|
||||
const int size = 2;
|
||||
@ -362,8 +358,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("INS <Vd>.D[<index>], X<n>")]
|
||||
public void Ins_Gp_XD([Values(0u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_X_")] [Random(RndCnt)] ulong xn,
|
||||
[ValueSource(nameof(_1D_))] ulong z,
|
||||
[ValueSource(nameof(_X_))] ulong xn,
|
||||
[Values(0u, 1u)] uint index)
|
||||
{
|
||||
const int size = 3;
|
||||
@ -385,10 +381,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("INS <Vd>.B[<index1>], <Vn>.B[<index2>]")]
|
||||
public void Ins_V_BB([Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
|
||||
[Values(0u, 15u)] [Random(1u, 14u, RndCntIndex)] uint dstIndex,
|
||||
[Values(0u, 15u)] [Random(1u, 14u, RndCntIndex)] uint srcIndex)
|
||||
[ValueSource(nameof(_8B_))] ulong z,
|
||||
[ValueSource(nameof(_8B_))] ulong a,
|
||||
[Values(0u, 15u)] uint dstIndex,
|
||||
[Values(0u, 15u)] uint srcIndex)
|
||||
{
|
||||
const int size = 0;
|
||||
|
||||
@ -411,10 +407,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("INS <Vd>.H[<index1>], <Vn>.H[<index2>]")]
|
||||
public void Ins_V_HH([Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
|
||||
[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint dstIndex,
|
||||
[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint srcIndex)
|
||||
[ValueSource(nameof(_4H_))] ulong z,
|
||||
[ValueSource(nameof(_4H_))] ulong a,
|
||||
[Values(0u, 7u)] uint dstIndex,
|
||||
[Values(0u, 7u)] uint srcIndex)
|
||||
{
|
||||
const int size = 1;
|
||||
|
||||
@ -437,8 +433,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("INS <Vd>.S[<index1>], <Vn>.S[<index2>]")]
|
||||
public void Ins_V_SS([Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
|
||||
[ValueSource(nameof(_2S_))] ulong z,
|
||||
[ValueSource(nameof(_2S_))] ulong a,
|
||||
[Values(0u, 1u, 2u, 3u)] uint dstIndex,
|
||||
[Values(0u, 1u, 2u, 3u)] uint srcIndex)
|
||||
{
|
||||
@ -463,8 +459,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("INS <Vd>.D[<index1>], <Vn>.D[<index2>]")]
|
||||
public void Ins_V_DD([Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
|
||||
[ValueSource(nameof(_1D_))] ulong z,
|
||||
[ValueSource(nameof(_1D_))] ulong a,
|
||||
[Values(0u, 1u)] uint dstIndex,
|
||||
[Values(0u, 1u)] uint srcIndex)
|
||||
{
|
||||
@ -489,8 +485,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("SMOV <Wd>, <Vn>.B[<index>]")]
|
||||
public void Smov_S_BW([Values(0u, 31u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
|
||||
[Values(0u, 15u)] [Random(1u, 14u, RndCntIndex)] uint index)
|
||||
[ValueSource(nameof(_8B_))] ulong a,
|
||||
[Values(0u, 15u)] uint index)
|
||||
{
|
||||
const int size = 0;
|
||||
|
||||
@ -512,8 +508,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("SMOV <Wd>, <Vn>.H[<index>]")]
|
||||
public void Smov_S_HW([Values(0u, 31u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
|
||||
[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index)
|
||||
[ValueSource(nameof(_4H_))] ulong a,
|
||||
[Values(0u, 7u)] uint index)
|
||||
{
|
||||
const int size = 1;
|
||||
|
||||
@ -535,8 +531,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("SMOV <Xd>, <Vn>.B[<index>]")]
|
||||
public void Smov_S_BX([Values(0u, 31u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
|
||||
[Values(0u, 15u)] [Random(1u, 14u, RndCntIndex)] uint index)
|
||||
[ValueSource(nameof(_8B_))] ulong a,
|
||||
[Values(0u, 15u)] uint index)
|
||||
{
|
||||
const int size = 0;
|
||||
|
||||
@ -557,8 +553,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("SMOV <Xd>, <Vn>.H[<index>]")]
|
||||
public void Smov_S_HX([Values(0u, 31u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
|
||||
[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index)
|
||||
[ValueSource(nameof(_4H_))] ulong a,
|
||||
[Values(0u, 7u)] uint index)
|
||||
{
|
||||
const int size = 1;
|
||||
|
||||
@ -579,7 +575,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("SMOV <Xd>, <Vn>.S[<index>]")]
|
||||
public void Smov_S_SX([Values(0u, 31u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
|
||||
[ValueSource(nameof(_2S_))] ulong a,
|
||||
[Values(0u, 1u, 2u, 3u)] uint index)
|
||||
{
|
||||
const int size = 2;
|
||||
@ -601,8 +597,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("UMOV <Wd>, <Vn>.B[<index>]")]
|
||||
public void Umov_S_BW([Values(0u, 31u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
|
||||
[Values(0u, 15u)] [Random(1u, 14u, RndCntIndex)] uint index)
|
||||
[ValueSource(nameof(_8B_))] ulong a,
|
||||
[Values(0u, 15u)] uint index)
|
||||
{
|
||||
const int size = 0;
|
||||
|
||||
@ -624,8 +620,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("UMOV <Wd>, <Vn>.H[<index>]")]
|
||||
public void Umov_S_HW([Values(0u, 31u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
|
||||
[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index)
|
||||
[ValueSource(nameof(_4H_))] ulong a,
|
||||
[Values(0u, 7u)] uint index)
|
||||
{
|
||||
const int size = 1;
|
||||
|
||||
@ -647,7 +643,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("UMOV <Wd>, <Vn>.S[<index>]")]
|
||||
public void Umov_S_SW([Values(0u, 31u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
|
||||
[ValueSource(nameof(_2S_))] ulong a,
|
||||
[Values(0u, 1u, 2u, 3u)] uint index)
|
||||
{
|
||||
const int size = 2;
|
||||
@ -670,7 +666,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("UMOV <Xd>, <Vn>.D[<index>]")]
|
||||
public void Umov_S_DX([Values(0u, 31u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
|
||||
[ValueSource(nameof(_1D_))] ulong a,
|
||||
[Values(0u, 1u)] uint index)
|
||||
{
|
||||
const int size = 3;
|
||||
@ -690,4 +686,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -13,17 +13,17 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Types)"
|
||||
private static ulong[] _8B4H2S_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
#endregion
|
||||
|
||||
#region "ValueSource (Opcodes)"
|
||||
private static uint[] _Vbic_Vbif_Vbit_Vbsl_Vand_Vorn_Vorr_Veor_I_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xf2100110u, // VBIC D0, D0, D0
|
||||
0xf3300110u, // VBIF D0, D0, D0
|
||||
@ -38,7 +38,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Vbic_Vorr_II_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xf2800130u, // VBIC.I32 D0, #0 (A1)
|
||||
0xf2800930u, // VBIC.I16 D0, #0 (A2)
|
||||
@ -48,16 +48,14 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endregion
|
||||
|
||||
private const int RndCnt = 2;
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Vbic_Vbif_Vbit_Vbsl_Vand_Vorn_Vorr_Veor_I([ValueSource("_Vbic_Vbif_Vbit_Vbsl_Vand_Vorn_Vorr_Veor_I_")] uint opcode,
|
||||
public void Vbic_Vbif_Vbit_Vbsl_Vand_Vorn_Vorr_Veor_I([ValueSource(nameof(_Vbic_Vbif_Vbit_Vbsl_Vand_Vorn_Vorr_Veor_I_))] uint opcode,
|
||||
[Range(0u, 5u)] uint rd,
|
||||
[Range(0u, 5u)] uint rn,
|
||||
[Range(0u, 5u)] uint rm,
|
||||
[Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong z,
|
||||
[Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong a,
|
||||
[Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong b,
|
||||
[Values(ulong.MinValue, ulong.MaxValue)] ulong z,
|
||||
[Values(ulong.MinValue, ulong.MaxValue)] ulong a,
|
||||
[Values(ulong.MinValue, ulong.MaxValue)] ulong b,
|
||||
[Values] bool q)
|
||||
{
|
||||
if (q)
|
||||
@ -83,10 +81,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Vbic_Vorr_II([ValueSource("_Vbic_Vorr_II_")] uint opcode,
|
||||
public void Vbic_Vorr_II([ValueSource(nameof(_Vbic_Vorr_II_))] uint opcode,
|
||||
[Values(0u, 1u)] uint rd,
|
||||
[Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong z,
|
||||
[Values(byte.MinValue, byte.MaxValue)] [Random(RndCnt)] byte imm,
|
||||
[Values(ulong.MinValue, ulong.MaxValue)] ulong z,
|
||||
[Values(byte.MinValue, byte.MaxValue)] byte imm,
|
||||
[Values(0u, 1u, 2u, 3u)] uint cMode,
|
||||
[Values] bool q)
|
||||
{
|
||||
@ -119,9 +117,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Vtst([Range(0u, 5u)] uint rd,
|
||||
[Range(0u, 5u)] uint rn,
|
||||
[Range(0u, 5u)] uint rm,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong a,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong b,
|
||||
[ValueSource(nameof(_8B4H2S_))] ulong z,
|
||||
[ValueSource(nameof(_8B4H2S_))] ulong a,
|
||||
[ValueSource(nameof(_8B4H2S_))] ulong b,
|
||||
[Values(0u, 1u, 2u)] uint size,
|
||||
[Values] bool q)
|
||||
{
|
||||
@ -152,4 +150,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -10,7 +10,6 @@ namespace Ryujinx.Tests.Cpu
|
||||
public sealed class CpuTestSimdMemory32 : CpuTest32
|
||||
{
|
||||
#if SimdMemory32
|
||||
private const int RndCntImm = 2;
|
||||
|
||||
private uint[] _ldStModes =
|
||||
{
|
||||
@ -41,7 +40,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd,
|
||||
[Range(0u, 7u)] uint index,
|
||||
[Range(0u, 3u)] uint n,
|
||||
[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
|
||||
[Values(0x0u)] uint offset)
|
||||
{
|
||||
var data = GenerateVectorSequence(0x1000);
|
||||
SetWorkingMemory(0, data);
|
||||
@ -71,7 +70,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Range(0u, 3u)] uint n,
|
||||
[Range(0u, 2u)] uint size,
|
||||
[Values] bool t,
|
||||
[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
|
||||
[Values(0x0u)] uint offset)
|
||||
{
|
||||
var data = GenerateVectorSequence(0x1000);
|
||||
SetWorkingMemory(0, data);
|
||||
@ -97,7 +96,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 13u, 15u)] uint rm,
|
||||
[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd,
|
||||
[Range(0u, 10u)] uint mode,
|
||||
[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
|
||||
[Values(0x0u)] uint offset)
|
||||
{
|
||||
var data = GenerateVectorSequence(0x1000);
|
||||
SetWorkingMemory(0, data);
|
||||
@ -127,7 +126,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd,
|
||||
[Range(0u, 7u)] uint index,
|
||||
[Range(0u, 3u)] uint n,
|
||||
[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
|
||||
[Values(0x0u)] uint offset)
|
||||
{
|
||||
var data = GenerateVectorSequence(0x1000);
|
||||
SetWorkingMemory(0, data);
|
||||
@ -158,7 +157,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Values(1u, 13u, 15u)] uint rm,
|
||||
[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd,
|
||||
[Range(0u, 10u)] uint mode,
|
||||
[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
|
||||
[Values(0x0u)] uint offset)
|
||||
{
|
||||
var data = GenerateVectorSequence(0x1000);
|
||||
SetWorkingMemory(0, data);
|
||||
@ -187,7 +186,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Vldm([Values(0u, 13u)] uint rn,
|
||||
[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd,
|
||||
[Range(0u, 2u)] uint mode,
|
||||
[Values(0x1u, 0x32u)] [Random(2u, 31u, RndCntImm)] uint regs,
|
||||
[Values(0x1u, 0x32u)] uint regs,
|
||||
[Values] bool single)
|
||||
{
|
||||
var data = GenerateVectorSequence(0x1000);
|
||||
@ -235,7 +234,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Vldr([Values(2u, 3u)] uint size, // FP16 is not supported for now
|
||||
[Values(0u)] uint rn,
|
||||
[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint sd,
|
||||
[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint imm,
|
||||
[Values(0x0u)] uint imm,
|
||||
[Values] bool sub)
|
||||
{
|
||||
var data = GenerateVectorSequence(0x1000);
|
||||
@ -270,7 +269,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Vstr([Values(2u, 3u)] uint size, // FP16 is not supported for now
|
||||
[Values(0u)] uint rn,
|
||||
[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint sd,
|
||||
[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint imm,
|
||||
[Values(0x0u)] uint imm,
|
||||
[Values] bool sub)
|
||||
{
|
||||
var data = GenerateVectorSequence(0x1000);
|
||||
@ -329,4 +328,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -14,7 +14,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("VMOV.I<size> <Dd/Qd>, #<imm>")]
|
||||
public void Movi_V([Range(0u, 10u)] uint variant,
|
||||
[Values(0u, 1u, 2u, 3u)] uint vd,
|
||||
[Values(0x0u)] [Random(1u, 0xffu, RndCntImm)] uint imm,
|
||||
[Values(0x0u)] uint imm,
|
||||
[Values] bool q)
|
||||
{
|
||||
uint[] variants =
|
||||
@ -62,7 +62,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("VMOV.F<size> <Sd>, #<imm>")]
|
||||
public void Movi_S([Range(2u, 3u)] uint size,
|
||||
[Values(0u, 1u, 2u, 3u)] uint vd,
|
||||
[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint imm)
|
||||
[Values(0x0u)] uint imm)
|
||||
{
|
||||
uint opcode = 0xeeb00800u;
|
||||
opcode |= (size & 3) << 8;
|
||||
@ -292,7 +292,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
[Test, Pairwise, Description("VMVN.I<size> <Dd/Qd>, #<imm>")]
|
||||
public void Mvni_V([Range(0u, 7u)] uint variant,
|
||||
[Values(0u, 1u, 2u, 3u)] uint vd,
|
||||
[Values(0x0u)] [Random(1u, 0xffu, RndCntImm)] uint imm,
|
||||
[Values(0x0u)] uint imm,
|
||||
[Values] bool q)
|
||||
{
|
||||
uint[] variants =
|
||||
@ -596,4 +596,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -14,7 +14,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Opcodes)"
|
||||
private static uint[] _V_Add_Sub_Long_Wide_I_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xf2800000u, // VADDL.S8 Q0, D0, D0
|
||||
0xf2800100u, // VADDW.S8 Q0, Q0, D0
|
||||
@ -25,7 +25,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Vfma_Vfms_Vfnma_Vfnms_S_F32_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xEEA00A00u, // VFMA. F32 S0, S0, S0
|
||||
0xEEA00A40u, // VFMS. F32 S0, S0, S0
|
||||
@ -36,7 +36,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Vfma_Vfms_Vfnma_Vfnms_S_F64_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xEEA00B00u, // VFMA. F64 D0, D0, D0
|
||||
0xEEA00B40u, // VFMS. F64 D0, D0, D0
|
||||
@ -47,7 +47,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Vfma_Vfms_V_F32_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xF2000C10u, // VFMA.F32 D0, D0, D0
|
||||
0xF2200C10u // VFMS.F32 D0, D0, D0
|
||||
@ -56,7 +56,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Vmla_Vmls_Vnmla_Vnmls_S_F32_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xEE000A00u, // VMLA. F32 S0, S0, S0
|
||||
0xEE000A40u, // VMLS. F32 S0, S0, S0
|
||||
@ -67,7 +67,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Vmla_Vmls_Vnmla_Vnmls_S_F64_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xEE000B00u, // VMLA. F64 D0, D0, D0
|
||||
0xEE000B40u, // VMLS. F64 D0, D0, D0
|
||||
@ -78,7 +78,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Vmlal_Vmlsl_V_I_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xf2800800u, // VMLAL.S8 Q0, D0, D0
|
||||
0xf2800a00u // VMLSL.S8 Q0, D0, D0
|
||||
@ -87,7 +87,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Vp_Add_Max_Min_F_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xf3000d00u, // VPADD.F32 D0, D0, D0
|
||||
0xf3000f00u, // VPMAX.F32 D0, D0, D0
|
||||
@ -97,7 +97,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Vp_Add_I_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xf2000b10u // VPADD.I8 D0, D0, D0
|
||||
};
|
||||
@ -105,7 +105,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _V_Pmax_Pmin_Rhadd_I_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xf2000a00u, // VPMAX .S8 D0, D0, D0
|
||||
0xf2000a10u, // VPMIN .S8 D0, D0, D0
|
||||
@ -115,7 +115,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Vq_Add_Sub_I_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xf2000050u, // VQADD.S8 Q0, Q0, Q0
|
||||
0xf2000250u // VQSUB.S8 Q0, Q0, Q0
|
||||
@ -126,18 +126,18 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Types)"
|
||||
private static ulong[] _8B1D_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _8B4H2S1D_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static IEnumerable<ulong> _1S_F_()
|
||||
@ -378,12 +378,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Vadd_F32([Values(0u)] uint rd,
|
||||
[Values(0u, 1u)] uint rn,
|
||||
[Values(0u, 2u)] uint rm,
|
||||
[ValueSource("_2S_F_")] ulong z0,
|
||||
[ValueSource("_2S_F_")] ulong z1,
|
||||
[ValueSource("_2S_F_")] ulong a0,
|
||||
[ValueSource("_2S_F_")] ulong a1,
|
||||
[ValueSource("_2S_F_")] ulong b0,
|
||||
[ValueSource("_2S_F_")] ulong b1,
|
||||
[ValueSource(nameof(_2S_F_))] ulong z0,
|
||||
[ValueSource(nameof(_2S_F_))] ulong z1,
|
||||
[ValueSource(nameof(_2S_F_))] ulong a0,
|
||||
[ValueSource(nameof(_2S_F_))] ulong a1,
|
||||
[ValueSource(nameof(_2S_F_))] ulong b0,
|
||||
[ValueSource(nameof(_2S_F_))] ulong b1,
|
||||
[Values] bool q)
|
||||
{
|
||||
uint opcode = 0xf2000d00u; // VADD.F32 D0, D0, D0
|
||||
@ -409,13 +409,13 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void V_Add_Sub_Long_Wide_I([ValueSource("_V_Add_Sub_Long_Wide_I_")] uint opcode,
|
||||
public void V_Add_Sub_Long_Wide_I([ValueSource(nameof(_V_Add_Sub_Long_Wide_I_))] uint opcode,
|
||||
[Range(0u, 5u)] uint rd,
|
||||
[Range(0u, 5u)] uint rn,
|
||||
[Range(0u, 5u)] uint rm,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong a,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong b,
|
||||
[ValueSource(nameof(_8B4H2S1D_))] ulong z,
|
||||
[ValueSource(nameof(_8B4H2S1D_))] ulong a,
|
||||
[ValueSource(nameof(_8B4H2S1D_))] ulong b,
|
||||
[Values(0u, 1u, 2u)] uint size, // <SU8, SU16, SU32>
|
||||
[Values] bool u) // <S, U>
|
||||
{
|
||||
@ -444,8 +444,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
[Test, Pairwise, Description("VCMP.f<size> Vd, Vm")]
|
||||
public void Vcmp([Values(2u, 3u)] uint size,
|
||||
[ValueSource("_1S_F_")] ulong a,
|
||||
[ValueSource("_1S_F_")] ulong b,
|
||||
[ValueSource(nameof(_1S_F_))] ulong a,
|
||||
[ValueSource(nameof(_1S_F_))] ulong b,
|
||||
[Values] bool e)
|
||||
{
|
||||
uint opcode = 0xeeb40840u;
|
||||
@ -666,8 +666,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Vmull_I_P8_P64([Values(0u, 1u)] uint rd,
|
||||
[Values(0u, 1u)] uint rn,
|
||||
[Values(0u, 1u)] uint rm,
|
||||
[ValueSource(nameof(_8B1D_))] [Random(RndCnt)] ulong d0,
|
||||
[ValueSource(nameof(_8B1D_))] [Random(RndCnt)] ulong d1,
|
||||
[ValueSource(nameof(_8B1D_))] ulong d0,
|
||||
[ValueSource(nameof(_8B1D_))] ulong d1,
|
||||
[Values(0u/*, 2u*/)] uint size) // <P8, P64>
|
||||
{
|
||||
/*if (size == 2u)
|
||||
@ -734,22 +734,21 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
[Explicit]
|
||||
[Test, Pairwise]
|
||||
public void Vp_Add_Max_Min_F([ValueSource("_Vp_Add_Max_Min_F_")] uint opcode,
|
||||
public void Vp_Add_Max_Min_F([ValueSource(nameof(_Vp_Add_Max_Min_F_))] uint opcode,
|
||||
[Values(0u)] uint rd,
|
||||
[Range(0u, 7u)] uint rn,
|
||||
[Range(0u, 7u)] uint rm,
|
||||
[ValueSource("_2S_F_")] ulong z0,
|
||||
[ValueSource("_2S_F_")] ulong z1,
|
||||
[ValueSource("_2S_F_")] ulong a0,
|
||||
[ValueSource("_2S_F_")] ulong a1,
|
||||
[ValueSource("_2S_F_")] ulong b0,
|
||||
[ValueSource("_2S_F_")] ulong b1)
|
||||
[ValueSource(nameof(_2S_F_))] ulong z0,
|
||||
[ValueSource(nameof(_2S_F_))] ulong z1,
|
||||
[ValueSource(nameof(_2S_F_))] ulong a0,
|
||||
[ValueSource(nameof(_2S_F_))] ulong a1,
|
||||
[ValueSource(nameof(_2S_F_))] ulong b0,
|
||||
[ValueSource(nameof(_2S_F_))] ulong b1)
|
||||
{
|
||||
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
|
||||
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
|
||||
opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
|
||||
|
||||
var rnd = TestContext.CurrentContext.Random;
|
||||
V128 v0 = MakeVectorE0E1(z0, z1);
|
||||
V128 v1 = MakeVectorE0E1(a0, a1);
|
||||
V128 v2 = MakeVectorE0E1(b0, b1);
|
||||
@ -760,7 +759,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Vp_Add_I([ValueSource("_Vp_Add_I_")] uint opcode,
|
||||
public void Vp_Add_I([ValueSource(nameof(_Vp_Add_I_))] uint opcode,
|
||||
[Values(0u)] uint rd,
|
||||
[Range(0u, 5u)] uint rn,
|
||||
[Range(0u, 5u)] uint rm,
|
||||
@ -785,7 +784,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void V_Pmax_Pmin_Rhadd_I([ValueSource("_V_Pmax_Pmin_Rhadd_I_")] uint opcode,
|
||||
public void V_Pmax_Pmin_Rhadd_I([ValueSource(nameof(_V_Pmax_Pmin_Rhadd_I_))] uint opcode,
|
||||
[Values(0u)] uint rd,
|
||||
[Range(0u, 5u)] uint rn,
|
||||
[Range(0u, 5u)] uint rm,
|
||||
@ -816,13 +815,13 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Vq_Add_Sub_I([ValueSource("_Vq_Add_Sub_I_")] uint opcode,
|
||||
public void Vq_Add_Sub_I([ValueSource(nameof(_Vq_Add_Sub_I_))] uint opcode,
|
||||
[Range(0u, 5u)] uint rd,
|
||||
[Range(0u, 5u)] uint rn,
|
||||
[Range(0u, 5u)] uint rm,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong a,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong b,
|
||||
[ValueSource(nameof(_8B4H2S1D_))] ulong z,
|
||||
[ValueSource(nameof(_8B4H2S1D_))] ulong a,
|
||||
[ValueSource(nameof(_8B4H2S1D_))] ulong b,
|
||||
[Values(0u, 1u, 2u)] uint size, // <SU8, SU16, SU32>
|
||||
[Values] bool u) // <S, U>
|
||||
{
|
||||
@ -854,9 +853,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Vqdmulh_I([Range(0u, 5u)] uint rd,
|
||||
[Range(0u, 5u)] uint rn,
|
||||
[Range(0u, 5u)] uint rm,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong a,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong b,
|
||||
[ValueSource(nameof(_8B4H2S1D_))] ulong z,
|
||||
[ValueSource(nameof(_8B4H2S1D_))] ulong a,
|
||||
[ValueSource(nameof(_8B4H2S1D_))] ulong b,
|
||||
[Values(1u, 2u)] uint size) // <S16, S32>
|
||||
{
|
||||
rd >>= 1; rd <<= 1;
|
||||
@ -881,4 +880,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,7 +1,6 @@
|
||||
#define SimdRegElem
|
||||
|
||||
using ARMeilleure.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
@ -14,21 +13,21 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Types)"
|
||||
private static ulong[] _2S_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _4H_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
#endregion
|
||||
|
||||
#region "ValueSource (Opcodes)"
|
||||
private static uint[] _Mla_Mls_Mul_Sqdmulh_Sqrdmulh_Ve_4H_8H_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x2F400000u, // MLA V0.4H, V0.4H, V0.H[0]
|
||||
0x2F404000u, // MLS V0.4H, V0.4H, V0.H[0]
|
||||
@ -40,7 +39,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Mla_Mls_Mul_Sqdmulh_Sqrdmulh_Ve_2S_4S_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x2F800000u, // MLA V0.2S, V0.2S, V0.S[0]
|
||||
0x2F804000u, // MLS V0.2S, V0.2S, V0.S[0]
|
||||
@ -52,7 +51,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _SU_Mlal_Mlsl_Mull_Ve_4H4S_8H4S_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F402000u, // SMLAL V0.4S, V0.4H, V0.H[0]
|
||||
0x0F406000u, // SMLSL V0.4S, V0.4H, V0.H[0]
|
||||
@ -65,7 +64,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _SU_Mlal_Mlsl_Mull_Ve_2S2D_4S2D_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F802000u, // SMLAL V0.2D, V0.2S, V0.S[0]
|
||||
0x0F806000u, // SMLSL V0.2D, V0.2S, V0.S[0]
|
||||
@ -77,18 +76,16 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endregion
|
||||
|
||||
private const int RndCnt = 2;
|
||||
private const int RndCntIndex = 2;
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Mla_Mls_Mul_Sqdmulh_Sqrdmulh_Ve_4H_8H([ValueSource(nameof(_Mla_Mls_Mul_Sqdmulh_Sqrdmulh_Ve_4H_8H_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[Values(2u, 0u)] uint rm,
|
||||
[ValueSource(nameof(_4H_))] [Random(RndCnt)] ulong z,
|
||||
[ValueSource(nameof(_4H_))] [Random(RndCnt)] ulong a,
|
||||
[ValueSource(nameof(_4H_))] [Random(RndCnt)] ulong b,
|
||||
[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index,
|
||||
[ValueSource(nameof(_4H_))] ulong z,
|
||||
[ValueSource(nameof(_4H_))] ulong a,
|
||||
[ValueSource(nameof(_4H_))] ulong b,
|
||||
[Values(0u, 7u)] uint index,
|
||||
[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
|
||||
{
|
||||
uint h = (index >> 2) & 1;
|
||||
@ -110,12 +107,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Mla_Mls_Mul_Sqdmulh_Sqrdmulh_Ve_2S_4S([ValueSource(nameof(_Mla_Mls_Mul_Sqdmulh_Sqrdmulh_Ve_2S_4S_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[Values(2u, 0u)] uint rm,
|
||||
[ValueSource(nameof(_2S_))] [Random(RndCnt)] ulong z,
|
||||
[ValueSource(nameof(_2S_))] [Random(RndCnt)] ulong a,
|
||||
[ValueSource(nameof(_2S_))] [Random(RndCnt)] ulong b,
|
||||
[ValueSource(nameof(_2S_))] ulong z,
|
||||
[ValueSource(nameof(_2S_))] ulong a,
|
||||
[ValueSource(nameof(_2S_))] ulong b,
|
||||
[Values(0u, 1u, 2u, 3u)] uint index,
|
||||
[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
|
||||
{
|
||||
@ -136,14 +133,14 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void SU_Mlal_Mlsl_Mull_Ve_4H4S_8H4S([ValueSource("_SU_Mlal_Mlsl_Mull_Ve_4H4S_8H4S_")] uint opcodes,
|
||||
public void SU_Mlal_Mlsl_Mull_Ve_4H4S_8H4S([ValueSource(nameof(_SU_Mlal_Mlsl_Mull_Ve_4H4S_8H4S_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[Values(2u, 0u)] uint rm,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong b,
|
||||
[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index,
|
||||
[ValueSource(nameof(_4H_))] ulong z,
|
||||
[ValueSource(nameof(_4H_))] ulong a,
|
||||
[ValueSource(nameof(_4H_))] ulong b,
|
||||
[Values(0u, 7u)] uint index,
|
||||
[Values(0b0u, 0b1u)] uint q) // <4H4S, 8H4S>
|
||||
{
|
||||
uint h = (index >> 2) & 1;
|
||||
@ -164,13 +161,13 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void SU_Mlal_Mlsl_Mull_Ve_2S2D_4S2D([ValueSource("_SU_Mlal_Mlsl_Mull_Ve_2S2D_4S2D_")] uint opcodes,
|
||||
public void SU_Mlal_Mlsl_Mull_Ve_2S2D_4S2D([ValueSource(nameof(_SU_Mlal_Mlsl_Mull_Ve_2S2D_4S2D_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[Values(2u, 0u)] uint rm,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong b,
|
||||
[ValueSource(nameof(_2S_))] ulong z,
|
||||
[ValueSource(nameof(_2S_))] ulong a,
|
||||
[ValueSource(nameof(_2S_))] ulong b,
|
||||
[Values(0u, 1u, 2u, 3u)] uint index,
|
||||
[Values(0b0u, 0b1u)] uint q) // <2S2D, 4S2D>
|
||||
{
|
||||
@ -191,4 +188,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,9 +1,7 @@
|
||||
#define SimdRegElemF
|
||||
|
||||
using ARMeilleure.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
using System.Collections.Generic;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
@ -142,7 +140,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Opcodes)"
|
||||
private static uint[] _F_Mla_Mls_Se_S_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x5F821020u, // FMLA S0, S1, V2.S[0]
|
||||
0x5F825020u // FMLS S0, S1, V2.S[0]
|
||||
@ -151,7 +149,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _F_Mla_Mls_Se_D_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x5FC21020u, // FMLA D0, D1, V2.D[0]
|
||||
0x5FC25020u // FMLS D0, D1, V2.D[0]
|
||||
@ -160,7 +158,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _F_Mla_Mls_Ve_2S_4S_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F801000u, // FMLA V0.2S, V0.2S, V0.S[0]
|
||||
0x0F805000u // FMLS V0.2S, V0.2S, V0.S[0]
|
||||
@ -169,7 +167,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _F_Mla_Mls_Ve_2D_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x4FC01000u, // FMLA V0.2D, V0.2D, V0.D[0]
|
||||
0x4FC05000u // FMLS V0.2D, V0.2D, V0.D[0]
|
||||
@ -178,7 +176,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _F_Mul_Mulx_Se_S_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x5F829020u, // FMUL S0, S1, V2.S[0]
|
||||
0x7F829020u // FMULX S0, S1, V2.S[0]
|
||||
@ -187,7 +185,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _F_Mul_Mulx_Se_D_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x5FC29020u, // FMUL D0, D1, V2.D[0]
|
||||
0x7FC29020u // FMULX D0, D1, V2.D[0]
|
||||
@ -196,7 +194,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _F_Mul_Mulx_Ve_2S_4S_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F809000u, // FMUL V0.2S, V0.2S, V0.S[0]
|
||||
0x2F809000u // FMULX V0.2S, V0.2S, V0.S[0]
|
||||
@ -205,7 +203,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _F_Mul_Mulx_Ve_2D_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x4FC09000u, // FMUL V0.2D, V0.2D, V0.D[0]
|
||||
0x6FC09000u // FMULX V0.2D, V0.2D, V0.D[0]
|
||||
@ -220,10 +218,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
private static readonly bool NoNaNs = false;
|
||||
|
||||
[Test, Pairwise] [Explicit] // Fused.
|
||||
public void F_Mla_Mls_Se_S([ValueSource("_F_Mla_Mls_Se_S_")] uint opcodes,
|
||||
[ValueSource("_1S_F_")] ulong z,
|
||||
[ValueSource("_1S_F_")] ulong a,
|
||||
[ValueSource("_2S_F_")] ulong b,
|
||||
public void F_Mla_Mls_Se_S([ValueSource(nameof(_F_Mla_Mls_Se_S_))] uint opcodes,
|
||||
[ValueSource(nameof(_1S_F_))] ulong z,
|
||||
[ValueSource(nameof(_1S_F_))] ulong a,
|
||||
[ValueSource(nameof(_2S_F_))] ulong b,
|
||||
[Values(0u, 1u, 2u, 3u)] uint index)
|
||||
{
|
||||
uint h = (index >> 1) & 1;
|
||||
@ -246,10 +244,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit] // Fused.
|
||||
public void F_Mla_Mls_Se_D([ValueSource("_F_Mla_Mls_Se_D_")] uint opcodes,
|
||||
[ValueSource("_1D_F_")] ulong z,
|
||||
[ValueSource("_1D_F_")] ulong a,
|
||||
[ValueSource("_1D_F_")] ulong b,
|
||||
public void F_Mla_Mls_Se_D([ValueSource(nameof(_F_Mla_Mls_Se_D_))] uint opcodes,
|
||||
[ValueSource(nameof(_1D_F_))] ulong z,
|
||||
[ValueSource(nameof(_1D_F_))] ulong a,
|
||||
[ValueSource(nameof(_1D_F_))] ulong b,
|
||||
[Values(0u, 1u)] uint index)
|
||||
{
|
||||
uint h = index & 1;
|
||||
@ -271,13 +269,13 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit] // Fused.
|
||||
public void F_Mla_Mls_Ve_2S_4S([ValueSource("_F_Mla_Mls_Ve_2S_4S_")] uint opcodes,
|
||||
public void F_Mla_Mls_Ve_2S_4S([ValueSource(nameof(_F_Mla_Mls_Ve_2S_4S_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[Values(2u, 0u)] uint rm,
|
||||
[ValueSource("_2S_F_")] ulong z,
|
||||
[ValueSource("_2S_F_")] ulong a,
|
||||
[ValueSource("_2S_F_")] ulong b,
|
||||
[ValueSource(nameof(_2S_F_))] ulong z,
|
||||
[ValueSource(nameof(_2S_F_))] ulong a,
|
||||
[ValueSource(nameof(_2S_F_))] ulong b,
|
||||
[Values(0u, 1u, 2u, 3u)] uint index,
|
||||
[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
|
||||
{
|
||||
@ -303,13 +301,13 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit] // Fused.
|
||||
public void F_Mla_Mls_Ve_2D([ValueSource("_F_Mla_Mls_Ve_2D_")] uint opcodes,
|
||||
public void F_Mla_Mls_Ve_2D([ValueSource(nameof(_F_Mla_Mls_Ve_2D_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[Values(2u, 0u)] uint rm,
|
||||
[ValueSource("_1D_F_")] ulong z,
|
||||
[ValueSource("_1D_F_")] ulong a,
|
||||
[ValueSource("_1D_F_")] ulong b,
|
||||
[ValueSource(nameof(_1D_F_))] ulong z,
|
||||
[ValueSource(nameof(_1D_F_))] ulong a,
|
||||
[ValueSource(nameof(_1D_F_))] ulong b,
|
||||
[Values(0u, 1u)] uint index)
|
||||
{
|
||||
uint h = index & 1;
|
||||
@ -332,9 +330,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Mul_Mulx_Se_S([ValueSource("_F_Mul_Mulx_Se_S_")] uint opcodes,
|
||||
[ValueSource("_1S_F_")] ulong a,
|
||||
[ValueSource("_2S_F_")] ulong b,
|
||||
public void F_Mul_Mulx_Se_S([ValueSource(nameof(_F_Mul_Mulx_Se_S_))] uint opcodes,
|
||||
[ValueSource(nameof(_1S_F_))] ulong a,
|
||||
[ValueSource(nameof(_2S_F_))] ulong b,
|
||||
[Values(0u, 1u, 2u, 3u)] uint index)
|
||||
{
|
||||
uint h = (index >> 1) & 1;
|
||||
@ -358,9 +356,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Mul_Mulx_Se_D([ValueSource("_F_Mul_Mulx_Se_D_")] uint opcodes,
|
||||
[ValueSource("_1D_F_")] ulong a,
|
||||
[ValueSource("_1D_F_")] ulong b,
|
||||
public void F_Mul_Mulx_Se_D([ValueSource(nameof(_F_Mul_Mulx_Se_D_))] uint opcodes,
|
||||
[ValueSource(nameof(_1D_F_))] ulong a,
|
||||
[ValueSource(nameof(_1D_F_))] ulong b,
|
||||
[Values(0u, 1u)] uint index)
|
||||
{
|
||||
uint h = index & 1;
|
||||
@ -383,13 +381,13 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Mul_Mulx_Ve_2S_4S([ValueSource("_F_Mul_Mulx_Ve_2S_4S_")] uint opcodes,
|
||||
public void F_Mul_Mulx_Ve_2S_4S([ValueSource(nameof(_F_Mul_Mulx_Ve_2S_4S_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[Values(2u, 0u)] uint rm,
|
||||
[ValueSource("_2S_F_")] ulong z,
|
||||
[ValueSource("_2S_F_")] ulong a,
|
||||
[ValueSource("_2S_F_")] ulong b,
|
||||
[ValueSource(nameof(_2S_F_))] ulong z,
|
||||
[ValueSource(nameof(_2S_F_))] ulong a,
|
||||
[ValueSource(nameof(_2S_F_))] ulong b,
|
||||
[Values(0u, 1u, 2u, 3u)] uint index,
|
||||
[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
|
||||
{
|
||||
@ -415,13 +413,13 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Mul_Mulx_Ve_2D([ValueSource("_F_Mul_Mulx_Ve_2D_")] uint opcodes,
|
||||
public void F_Mul_Mulx_Ve_2D([ValueSource(nameof(_F_Mul_Mulx_Ve_2D_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[Values(2u, 0u)] uint rm,
|
||||
[ValueSource("_1D_F_")] ulong z,
|
||||
[ValueSource("_1D_F_")] ulong a,
|
||||
[ValueSource("_1D_F_")] ulong b,
|
||||
[ValueSource(nameof(_1D_F_))] ulong z,
|
||||
[ValueSource(nameof(_1D_F_))] ulong a,
|
||||
[ValueSource(nameof(_1D_F_))] ulong b,
|
||||
[Values(0u, 1u)] uint index)
|
||||
{
|
||||
uint h = index & 1;
|
||||
|
||||
@ -1,9 +1,7 @@
|
||||
#define SimdShImm
|
||||
|
||||
using ARMeilleure.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
using System;
|
||||
using System.Collections.Generic;
|
||||
|
||||
@ -17,38 +15,38 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Types)"
|
||||
private static ulong[] _1D_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _1H_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x0000000000007FFFul,
|
||||
0x0000000000008000ul, 0x000000000000FFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x0000000000007FFFul,
|
||||
0x0000000000008000ul, 0x000000000000FFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _1S_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x000000007FFFFFFFul,
|
||||
0x0000000080000000ul, 0x00000000FFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x000000007FFFFFFFul,
|
||||
0x0000000080000000ul, 0x00000000FFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _2S_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _4H_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _8B_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static IEnumerable<ulong> _2S_F_W_()
|
||||
@ -97,10 +95,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
for (int cnt = 1; cnt <= RndCnt; cnt++)
|
||||
{
|
||||
ulong rnd1 = (uint)BitConverter.SingleToInt32Bits(
|
||||
(float)((int)TestContext.CurrentContext.Random.NextUInt()));
|
||||
ulong rnd2 = (uint)BitConverter.SingleToInt32Bits(
|
||||
(float)((uint)TestContext.CurrentContext.Random.NextUInt()));
|
||||
ulong rnd1 = (uint)BitConverter.SingleToInt32Bits((int)TestContext.CurrentContext.Random.NextUInt());
|
||||
ulong rnd2 = (uint)BitConverter.SingleToInt32Bits(TestContext.CurrentContext.Random.NextUInt());
|
||||
|
||||
ulong rnd3 = GenNormalS();
|
||||
ulong rnd4 = GenSubnormalS();
|
||||
@ -160,9 +156,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
for (int cnt = 1; cnt <= RndCnt; cnt++)
|
||||
{
|
||||
ulong rnd1 = (ulong)BitConverter.DoubleToInt64Bits(
|
||||
(double)((long)TestContext.CurrentContext.Random.NextULong()));
|
||||
(long)TestContext.CurrentContext.Random.NextULong());
|
||||
ulong rnd2 = (ulong)BitConverter.DoubleToInt64Bits(
|
||||
(double)((ulong)TestContext.CurrentContext.Random.NextULong()));
|
||||
TestContext.CurrentContext.Random.NextULong());
|
||||
|
||||
ulong rnd3 = GenNormalD();
|
||||
ulong rnd4 = GenSubnormalD();
|
||||
@ -179,7 +175,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Opcodes)"
|
||||
private static uint[] _F_Cvt_Z_SU_V_Fixed_2S_4S_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F20FC00u, // FCVTZS V0.2S, V0.2S, #32
|
||||
0x2F20FC00u // FCVTZU V0.2S, V0.2S, #32
|
||||
@ -188,7 +184,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _F_Cvt_Z_SU_V_Fixed_2D_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x4F40FC00u, // FCVTZS V0.2D, V0.2D, #64
|
||||
0x6F40FC00u // FCVTZU V0.2D, V0.2D, #64
|
||||
@ -197,7 +193,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _SU_Cvt_F_S_Fixed_S_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x5F20E420u, // SCVTF S0, S1, #32
|
||||
0x7F20E420u // UCVTF S0, S1, #32
|
||||
@ -206,7 +202,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _SU_Cvt_F_S_Fixed_D_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x5F40E420u, // SCVTF D0, D1, #64
|
||||
0x7F40E420u // UCVTF D0, D1, #64
|
||||
@ -215,7 +211,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _SU_Cvt_F_V_Fixed_2S_4S_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F20E400u, // SCVTF V0.2S, V0.2S, #32
|
||||
0x2F20E400u // UCVTF V0.2S, V0.2S, #32
|
||||
@ -224,7 +220,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _SU_Cvt_F_V_Fixed_2D_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x4F40E400u, // SCVTF V0.2D, V0.2D, #64
|
||||
0x6F40E400u // UCVTF V0.2D, V0.2D, #64
|
||||
@ -233,7 +229,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Shl_Sli_S_D_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x5F405400u, // SHL D0, D0, #0
|
||||
0x7F405400u // SLI D0, D0, #0
|
||||
@ -242,7 +238,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Shl_Sli_V_8B_16B_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F085400u, // SHL V0.8B, V0.8B, #0
|
||||
0x2F085400u // SLI V0.8B, V0.8B, #0
|
||||
@ -251,7 +247,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Shl_Sli_V_4H_8H_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F105400u, // SHL V0.4H, V0.4H, #0
|
||||
0x2F105400u // SLI V0.4H, V0.4H, #0
|
||||
@ -260,7 +256,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Shl_Sli_V_2S_4S_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F205400u, // SHL V0.2S, V0.2S, #0
|
||||
0x2F205400u // SLI V0.2S, V0.2S, #0
|
||||
@ -269,7 +265,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Shl_Sli_V_2D_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x4F405400u, // SHL V0.2D, V0.2D, #0
|
||||
0x6F405400u // SLI V0.2D, V0.2D, #0
|
||||
@ -278,7 +274,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _SU_Shll_V_8B8H_16B8H_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F08A400u, // SSHLL V0.8H, V0.8B, #0
|
||||
0x2F08A400u // USHLL V0.8H, V0.8B, #0
|
||||
@ -287,7 +283,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _SU_Shll_V_4H4S_8H4S_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F10A400u, // SSHLL V0.4S, V0.4H, #0
|
||||
0x2F10A400u // USHLL V0.4S, V0.4H, #0
|
||||
@ -296,7 +292,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _SU_Shll_V_2S2D_4S2D_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F20A400u, // SSHLL V0.2D, V0.2S, #0
|
||||
0x2F20A400u // USHLL V0.2D, V0.2S, #0
|
||||
@ -305,7 +301,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _ShrImm_Sri_S_D_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x7F404400u, // SRI D0, D0, #64
|
||||
0x5F402400u, // SRSHR D0, D0, #64
|
||||
@ -321,7 +317,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _ShrImm_Sri_V_8B_16B_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x2F084400u, // SRI V0.8B, V0.8B, #8
|
||||
0x0F082400u, // SRSHR V0.8B, V0.8B, #8
|
||||
@ -337,7 +333,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _ShrImm_Sri_V_4H_8H_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x2F104400u, // SRI V0.4H, V0.4H, #16
|
||||
0x0F102400u, // SRSHR V0.4H, V0.4H, #16
|
||||
@ -353,7 +349,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _ShrImm_Sri_V_2S_4S_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x2F204400u, // SRI V0.2S, V0.2S, #32
|
||||
0x0F202400u, // SRSHR V0.2S, V0.2S, #32
|
||||
@ -369,7 +365,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _ShrImm_Sri_V_2D_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x6F404400u, // SRI V0.2D, V0.2D, #64
|
||||
0x4F402400u, // SRSHR V0.2D, V0.2D, #64
|
||||
@ -385,7 +381,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _ShrImmNarrow_V_8H8B_8H16B_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F088C00u, // RSHRN V0.8B, V0.8H, #8
|
||||
0x0F088400u // SHRN V0.8B, V0.8H, #8
|
||||
@ -394,7 +390,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _ShrImmNarrow_V_4S4H_4S8H_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F108C00u, // RSHRN V0.4H, V0.4S, #16
|
||||
0x0F108400u // SHRN V0.4H, V0.4S, #16
|
||||
@ -403,7 +399,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _ShrImmNarrow_V_2D2S_2D4S_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F208C00u, // RSHRN V0.2S, V0.2D, #32
|
||||
0x0F208400u // SHRN V0.2S, V0.2D, #32
|
||||
@ -412,7 +408,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _ShrImmSaturatingNarrow_S_HB_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x5F089C00u, // SQRSHRN B0, H0, #8
|
||||
0x7F089C00u, // UQRSHRN B0, H0, #8
|
||||
@ -425,7 +421,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _ShrImmSaturatingNarrow_S_SH_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x5F109C00u, // SQRSHRN H0, S0, #16
|
||||
0x7F109C00u, // UQRSHRN H0, S0, #16
|
||||
@ -438,7 +434,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _ShrImmSaturatingNarrow_S_DS_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x5F209C00u, // SQRSHRN S0, D0, #32
|
||||
0x7F209C00u, // UQRSHRN S0, D0, #32
|
||||
@ -451,7 +447,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _ShrImmSaturatingNarrow_V_8H8B_8H16B_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F089C00u, // SQRSHRN V0.8B, V0.8H, #8
|
||||
0x2F089C00u, // UQRSHRN V0.8B, V0.8H, #8
|
||||
@ -464,7 +460,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _ShrImmSaturatingNarrow_V_4S4H_4S8H_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F109C00u, // SQRSHRN V0.4H, V0.4S, #16
|
||||
0x2F109C00u, // UQRSHRN V0.4H, V0.4S, #16
|
||||
@ -477,7 +473,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _ShrImmSaturatingNarrow_V_2D2S_2D4S_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0F209C00u, // SQRSHRN V0.2S, V0.2D, #32
|
||||
0x2F209C00u, // UQRSHRN V0.2S, V0.2D, #32
|
||||
@ -490,20 +486,18 @@ namespace Ryujinx.Tests.Cpu
|
||||
#endregion
|
||||
|
||||
private const int RndCnt = 2;
|
||||
private const int RndCntFBits = 2;
|
||||
private const int RndCntShift = 2;
|
||||
|
||||
private static readonly bool NoZeros = false;
|
||||
private static readonly bool NoInfs = false;
|
||||
private static readonly bool NoNaNs = false;
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Cvt_Z_SU_V_Fixed_2S_4S([ValueSource("_F_Cvt_Z_SU_V_Fixed_2S_4S_")] uint opcodes,
|
||||
public void F_Cvt_Z_SU_V_Fixed_2S_4S([ValueSource(nameof(_F_Cvt_Z_SU_V_Fixed_2S_4S_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_2S_F_W_")] ulong z,
|
||||
[ValueSource("_2S_F_W_")] ulong a,
|
||||
[Values(1u, 32u)] [Random(2u, 31u, RndCntFBits)] uint fBits,
|
||||
[ValueSource(nameof(_2S_F_W_))] ulong z,
|
||||
[ValueSource(nameof(_2S_F_W_))] ulong a,
|
||||
[Values(1u, 32u)] uint fBits,
|
||||
[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
|
||||
{
|
||||
uint immHb = (64 - fBits) & 0x7F;
|
||||
@ -521,12 +515,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void F_Cvt_Z_SU_V_Fixed_2D([ValueSource("_F_Cvt_Z_SU_V_Fixed_2D_")] uint opcodes,
|
||||
public void F_Cvt_Z_SU_V_Fixed_2D([ValueSource(nameof(_F_Cvt_Z_SU_V_Fixed_2D_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_1D_F_X_")] ulong z,
|
||||
[ValueSource("_1D_F_X_")] ulong a,
|
||||
[Values(1u, 64u)] [Random(2u, 63u, RndCntFBits)] uint fBits)
|
||||
[ValueSource(nameof(_1D_F_X_))] ulong z,
|
||||
[ValueSource(nameof(_1D_F_X_))] ulong a,
|
||||
[Values(1u, 64u)] uint fBits)
|
||||
{
|
||||
uint immHb = (128 - fBits) & 0x7F;
|
||||
|
||||
@ -542,9 +536,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void SU_Cvt_F_S_Fixed_S([ValueSource("_SU_Cvt_F_S_Fixed_S_")] uint opcodes,
|
||||
[ValueSource("_1S_")] [Random(RndCnt)] ulong a,
|
||||
[Values(1u, 32u)] [Random(2u, 31u, RndCntFBits)] uint fBits)
|
||||
public void SU_Cvt_F_S_Fixed_S([ValueSource(nameof(_SU_Cvt_F_S_Fixed_S_))] uint opcodes,
|
||||
[ValueSource(nameof(_1S_))] ulong a,
|
||||
[Values(1u, 32u)] uint fBits)
|
||||
{
|
||||
uint immHb = (64 - fBits) & 0x7F;
|
||||
|
||||
@ -560,9 +554,9 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void SU_Cvt_F_S_Fixed_D([ValueSource("_SU_Cvt_F_S_Fixed_D_")] uint opcodes,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
|
||||
[Values(1u, 64u)] [Random(2u, 63u, RndCntFBits)] uint fBits)
|
||||
public void SU_Cvt_F_S_Fixed_D([ValueSource(nameof(_SU_Cvt_F_S_Fixed_D_))] uint opcodes,
|
||||
[ValueSource(nameof(_1D_))] ulong a,
|
||||
[Values(1u, 64u)] uint fBits)
|
||||
{
|
||||
uint immHb = (128 - fBits) & 0x7F;
|
||||
|
||||
@ -578,12 +572,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void SU_Cvt_F_V_Fixed_2S_4S([ValueSource("_SU_Cvt_F_V_Fixed_2S_4S_")] uint opcodes,
|
||||
public void SU_Cvt_F_V_Fixed_2S_4S([ValueSource(nameof(_SU_Cvt_F_V_Fixed_2S_4S_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
|
||||
[Values(1u, 32u)] [Random(2u, 31u, RndCntFBits)] uint fBits,
|
||||
[ValueSource(nameof(_2S_))] ulong z,
|
||||
[ValueSource(nameof(_2S_))] ulong a,
|
||||
[Values(1u, 32u)] uint fBits,
|
||||
[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
|
||||
{
|
||||
uint immHb = (64 - fBits) & 0x7F;
|
||||
@ -601,12 +595,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void SU_Cvt_F_V_Fixed_2D([ValueSource("_SU_Cvt_F_V_Fixed_2D_")] uint opcodes,
|
||||
public void SU_Cvt_F_V_Fixed_2D([ValueSource(nameof(_SU_Cvt_F_V_Fixed_2D_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
|
||||
[Values(1u, 64u)] [Random(2u, 63u, RndCntFBits)] uint fBits)
|
||||
[ValueSource(nameof(_1D_))] ulong z,
|
||||
[ValueSource(nameof(_1D_))] ulong a,
|
||||
[Values(1u, 64u)] uint fBits)
|
||||
{
|
||||
uint immHb = (128 - fBits) & 0x7F;
|
||||
|
||||
@ -622,12 +616,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Shl_Sli_S_D([ValueSource("_Shl_Sli_S_D_")] uint opcodes,
|
||||
public void Shl_Sli_S_D([ValueSource(nameof(_Shl_Sli_S_D_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
|
||||
[Values(0u, 63u)] [Random(1u, 62u, RndCntShift)] uint shift)
|
||||
[ValueSource(nameof(_1D_))] ulong z,
|
||||
[ValueSource(nameof(_1D_))] ulong a,
|
||||
[Values(0u, 63u)] uint shift)
|
||||
{
|
||||
uint immHb = (64 + shift) & 0x7F;
|
||||
|
||||
@ -643,12 +637,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Shl_Sli_V_8B_16B([ValueSource("_Shl_Sli_V_8B_16B_")] uint opcodes,
|
||||
public void Shl_Sli_V_8B_16B([ValueSource(nameof(_Shl_Sli_V_8B_16B_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
|
||||
[Values(0u, 7u)] [Random(1u, 6u, RndCntShift)] uint shift,
|
||||
[ValueSource(nameof(_8B_))] ulong z,
|
||||
[ValueSource(nameof(_8B_))] ulong a,
|
||||
[Values(0u, 7u)] uint shift,
|
||||
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
|
||||
{
|
||||
uint immHb = (8 + shift) & 0x7F;
|
||||
@ -666,12 +660,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Shl_Sli_V_4H_8H([ValueSource("_Shl_Sli_V_4H_8H_")] uint opcodes,
|
||||
public void Shl_Sli_V_4H_8H([ValueSource(nameof(_Shl_Sli_V_4H_8H_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
|
||||
[Values(0u, 15u)] [Random(1u, 14u, RndCntShift)] uint shift,
|
||||
[ValueSource(nameof(_4H_))] ulong z,
|
||||
[ValueSource(nameof(_4H_))] ulong a,
|
||||
[Values(0u, 15u)] uint shift,
|
||||
[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
|
||||
{
|
||||
uint immHb = (16 + shift) & 0x7F;
|
||||
@ -689,12 +683,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Shl_Sli_V_2S_4S([ValueSource("_Shl_Sli_V_2S_4S_")] uint opcodes,
|
||||
public void Shl_Sli_V_2S_4S([ValueSource(nameof(_Shl_Sli_V_2S_4S_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
|
||||
[Values(0u, 31u)] [Random(1u, 30u, RndCntShift)] uint shift,
|
||||
[ValueSource(nameof(_2S_))] ulong z,
|
||||
[ValueSource(nameof(_2S_))] ulong a,
|
||||
[Values(0u, 31u)] uint shift,
|
||||
[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
|
||||
{
|
||||
uint immHb = (32 + shift) & 0x7F;
|
||||
@ -712,12 +706,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Shl_Sli_V_2D([ValueSource("_Shl_Sli_V_2D_")] uint opcodes,
|
||||
public void Shl_Sli_V_2D([ValueSource(nameof(_Shl_Sli_V_2D_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
|
||||
[Values(0u, 63u)] [Random(1u, 62u, RndCntShift)] uint shift)
|
||||
[ValueSource(nameof(_1D_))] ulong z,
|
||||
[ValueSource(nameof(_1D_))] ulong a,
|
||||
[Values(0u, 63u)] uint shift)
|
||||
{
|
||||
uint immHb = (64 + shift) & 0x7F;
|
||||
|
||||
@ -733,12 +727,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void SU_Shll_V_8B8H_16B8H([ValueSource("_SU_Shll_V_8B8H_16B8H_")] uint opcodes,
|
||||
public void SU_Shll_V_8B8H_16B8H([ValueSource(nameof(_SU_Shll_V_8B8H_16B8H_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
|
||||
[Values(0u, 7u)] [Random(1u, 6u, RndCntShift)] uint shift,
|
||||
[ValueSource(nameof(_8B_))] ulong z,
|
||||
[ValueSource(nameof(_8B_))] ulong a,
|
||||
[Values(0u, 7u)] uint shift,
|
||||
[Values(0b0u, 0b1u)] uint q) // <8B8H, 16B8H>
|
||||
{
|
||||
uint immHb = (8 + shift) & 0x7F;
|
||||
@ -756,12 +750,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void SU_Shll_V_4H4S_8H4S([ValueSource("_SU_Shll_V_4H4S_8H4S_")] uint opcodes,
|
||||
public void SU_Shll_V_4H4S_8H4S([ValueSource(nameof(_SU_Shll_V_4H4S_8H4S_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
|
||||
[Values(0u, 15u)] [Random(1u, 14u, RndCntShift)] uint shift,
|
||||
[ValueSource(nameof(_4H_))] ulong z,
|
||||
[ValueSource(nameof(_4H_))] ulong a,
|
||||
[Values(0u, 15u)] uint shift,
|
||||
[Values(0b0u, 0b1u)] uint q) // <4H4S, 8H4S>
|
||||
{
|
||||
uint immHb = (16 + shift) & 0x7F;
|
||||
@ -779,12 +773,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void SU_Shll_V_2S2D_4S2D([ValueSource("_SU_Shll_V_2S2D_4S2D_")] uint opcodes,
|
||||
public void SU_Shll_V_2S2D_4S2D([ValueSource(nameof(_SU_Shll_V_2S2D_4S2D_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
|
||||
[Values(0u, 31u)] [Random(1u, 30u, RndCntShift)] uint shift,
|
||||
[ValueSource(nameof(_2S_))] ulong z,
|
||||
[ValueSource(nameof(_2S_))] ulong a,
|
||||
[Values(0u, 31u)] uint shift,
|
||||
[Values(0b0u, 0b1u)] uint q) // <2S2D, 4S2D>
|
||||
{
|
||||
uint immHb = (32 + shift) & 0x7F;
|
||||
@ -802,12 +796,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void ShrImm_Sri_S_D([ValueSource("_ShrImm_Sri_S_D_")] uint opcodes,
|
||||
public void ShrImm_Sri_S_D([ValueSource(nameof(_ShrImm_Sri_S_D_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
|
||||
[Values(1u, 64u)] [Random(2u, 63u, RndCntShift)] uint shift)
|
||||
[ValueSource(nameof(_1D_))] ulong z,
|
||||
[ValueSource(nameof(_1D_))] ulong a,
|
||||
[Values(1u, 64u)] uint shift)
|
||||
{
|
||||
uint immHb = (128 - shift) & 0x7F;
|
||||
|
||||
@ -823,12 +817,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void ShrImm_Sri_V_8B_16B([ValueSource("_ShrImm_Sri_V_8B_16B_")] uint opcodes,
|
||||
public void ShrImm_Sri_V_8B_16B([ValueSource(nameof(_ShrImm_Sri_V_8B_16B_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
|
||||
[Values(1u, 8u)] [Random(2u, 7u, RndCntShift)] uint shift,
|
||||
[ValueSource(nameof(_8B_))] ulong z,
|
||||
[ValueSource(nameof(_8B_))] ulong a,
|
||||
[Values(1u, 8u)] uint shift,
|
||||
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
|
||||
{
|
||||
uint immHb = (16 - shift) & 0x7F;
|
||||
@ -846,12 +840,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void ShrImm_Sri_V_4H_8H([ValueSource("_ShrImm_Sri_V_4H_8H_")] uint opcodes,
|
||||
public void ShrImm_Sri_V_4H_8H([ValueSource(nameof(_ShrImm_Sri_V_4H_8H_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
|
||||
[Values(1u, 16u)] [Random(2u, 15u, RndCntShift)] uint shift,
|
||||
[ValueSource(nameof(_4H_))] ulong z,
|
||||
[ValueSource(nameof(_4H_))] ulong a,
|
||||
[Values(1u, 16u)] uint shift,
|
||||
[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
|
||||
{
|
||||
uint immHb = (32 - shift) & 0x7F;
|
||||
@ -869,12 +863,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void ShrImm_Sri_V_2S_4S([ValueSource("_ShrImm_Sri_V_2S_4S_")] uint opcodes,
|
||||
public void ShrImm_Sri_V_2S_4S([ValueSource(nameof(_ShrImm_Sri_V_2S_4S_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
|
||||
[Values(1u, 32u)] [Random(2u, 31u, RndCntShift)] uint shift,
|
||||
[ValueSource(nameof(_2S_))] ulong z,
|
||||
[ValueSource(nameof(_2S_))] ulong a,
|
||||
[Values(1u, 32u)] uint shift,
|
||||
[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
|
||||
{
|
||||
uint immHb = (64 - shift) & 0x7F;
|
||||
@ -892,12 +886,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void ShrImm_Sri_V_2D([ValueSource("_ShrImm_Sri_V_2D_")] uint opcodes,
|
||||
public void ShrImm_Sri_V_2D([ValueSource(nameof(_ShrImm_Sri_V_2D_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
|
||||
[Values(1u, 64u)] [Random(2u, 63u, RndCntShift)] uint shift)
|
||||
[ValueSource(nameof(_1D_))] ulong z,
|
||||
[ValueSource(nameof(_1D_))] ulong a,
|
||||
[Values(1u, 64u)] uint shift)
|
||||
{
|
||||
uint immHb = (128 - shift) & 0x7F;
|
||||
|
||||
@ -913,12 +907,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void ShrImmNarrow_V_8H8B_8H16B([ValueSource("_ShrImmNarrow_V_8H8B_8H16B_")] uint opcodes,
|
||||
public void ShrImmNarrow_V_8H8B_8H16B([ValueSource(nameof(_ShrImmNarrow_V_8H8B_8H16B_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
|
||||
[Values(1u, 8u)] [Random(2u, 7u, RndCntShift)] uint shift,
|
||||
[ValueSource(nameof(_4H_))] ulong z,
|
||||
[ValueSource(nameof(_4H_))] ulong a,
|
||||
[Values(1u, 8u)] uint shift,
|
||||
[Values(0b0u, 0b1u)] uint q) // <8H8B, 8H16B>
|
||||
{
|
||||
uint immHb = (16 - shift) & 0x7F;
|
||||
@ -936,12 +930,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void ShrImmNarrow_V_4S4H_4S8H([ValueSource("_ShrImmNarrow_V_4S4H_4S8H_")] uint opcodes,
|
||||
public void ShrImmNarrow_V_4S4H_4S8H([ValueSource(nameof(_ShrImmNarrow_V_4S4H_4S8H_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
|
||||
[Values(1u, 16u)] [Random(2u, 15u, RndCntShift)] uint shift,
|
||||
[ValueSource(nameof(_2S_))] ulong z,
|
||||
[ValueSource(nameof(_2S_))] ulong a,
|
||||
[Values(1u, 16u)] uint shift,
|
||||
[Values(0b0u, 0b1u)] uint q) // <4S4H, 4S8H>
|
||||
{
|
||||
uint immHb = (32 - shift) & 0x7F;
|
||||
@ -959,12 +953,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void ShrImmNarrow_V_2D2S_2D4S([ValueSource("_ShrImmNarrow_V_2D2S_2D4S_")] uint opcodes,
|
||||
public void ShrImmNarrow_V_2D2S_2D4S([ValueSource(nameof(_ShrImmNarrow_V_2D2S_2D4S_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
|
||||
[Values(1u, 32u)] [Random(2u, 31u, RndCntShift)] uint shift,
|
||||
[ValueSource(nameof(_1D_))] ulong z,
|
||||
[ValueSource(nameof(_1D_))] ulong a,
|
||||
[Values(1u, 32u)] uint shift,
|
||||
[Values(0b0u, 0b1u)] uint q) // <2D2S, 2D4S>
|
||||
{
|
||||
uint immHb = (64 - shift) & 0x7F;
|
||||
@ -982,12 +976,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void ShrImmSaturatingNarrow_S_HB([ValueSource("_ShrImmSaturatingNarrow_S_HB_")] uint opcodes,
|
||||
public void ShrImmSaturatingNarrow_S_HB([ValueSource(nameof(_ShrImmSaturatingNarrow_S_HB_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_1H_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_1H_")] [Random(RndCnt)] ulong a,
|
||||
[Values(1u, 8u)] [Random(2u, 7u, RndCntShift)] uint shift)
|
||||
[ValueSource(nameof(_1H_))] ulong z,
|
||||
[ValueSource(nameof(_1H_))] ulong a,
|
||||
[Values(1u, 8u)] uint shift)
|
||||
{
|
||||
uint immHb = (16 - shift) & 0x7F;
|
||||
|
||||
@ -1003,12 +997,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void ShrImmSaturatingNarrow_S_SH([ValueSource("_ShrImmSaturatingNarrow_S_SH_")] uint opcodes,
|
||||
public void ShrImmSaturatingNarrow_S_SH([ValueSource(nameof(_ShrImmSaturatingNarrow_S_SH_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_1S_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_1S_")] [Random(RndCnt)] ulong a,
|
||||
[Values(1u, 16u)] [Random(2u, 15u, RndCntShift)] uint shift)
|
||||
[ValueSource(nameof(_1S_))] ulong z,
|
||||
[ValueSource(nameof(_1S_))] ulong a,
|
||||
[Values(1u, 16u)] uint shift)
|
||||
{
|
||||
uint immHb = (32 - shift) & 0x7F;
|
||||
|
||||
@ -1024,12 +1018,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void ShrImmSaturatingNarrow_S_DS([ValueSource("_ShrImmSaturatingNarrow_S_DS_")] uint opcodes,
|
||||
public void ShrImmSaturatingNarrow_S_DS([ValueSource(nameof(_ShrImmSaturatingNarrow_S_DS_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
|
||||
[Values(1u, 32u)] [Random(2u, 31u, RndCntShift)] uint shift)
|
||||
[ValueSource(nameof(_1D_))] ulong z,
|
||||
[ValueSource(nameof(_1D_))] ulong a,
|
||||
[Values(1u, 32u)] uint shift)
|
||||
{
|
||||
uint immHb = (64 - shift) & 0x7F;
|
||||
|
||||
@ -1045,12 +1039,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void ShrImmSaturatingNarrow_V_8H8B_8H16B([ValueSource("_ShrImmSaturatingNarrow_V_8H8B_8H16B_")] uint opcodes,
|
||||
public void ShrImmSaturatingNarrow_V_8H8B_8H16B([ValueSource(nameof(_ShrImmSaturatingNarrow_V_8H8B_8H16B_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
|
||||
[Values(1u, 8u)] [Random(2u, 7u, RndCntShift)] uint shift,
|
||||
[ValueSource(nameof(_4H_))] ulong z,
|
||||
[ValueSource(nameof(_4H_))] ulong a,
|
||||
[Values(1u, 8u)] uint shift,
|
||||
[Values(0b0u, 0b1u)] uint q) // <8H8B, 8H16B>
|
||||
{
|
||||
uint immHb = (16 - shift) & 0x7F;
|
||||
@ -1068,12 +1062,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void ShrImmSaturatingNarrow_V_4S4H_4S8H([ValueSource("_ShrImmSaturatingNarrow_V_4S4H_4S8H_")] uint opcodes,
|
||||
public void ShrImmSaturatingNarrow_V_4S4H_4S8H([ValueSource(nameof(_ShrImmSaturatingNarrow_V_4S4H_4S8H_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
|
||||
[Values(1u, 16u)] [Random(2u, 15u, RndCntShift)] uint shift,
|
||||
[ValueSource(nameof(_2S_))] ulong z,
|
||||
[ValueSource(nameof(_2S_))] ulong a,
|
||||
[Values(1u, 16u)] uint shift,
|
||||
[Values(0b0u, 0b1u)] uint q) // <4S4H, 4S8H>
|
||||
{
|
||||
uint immHb = (32 - shift) & 0x7F;
|
||||
@ -1091,12 +1085,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void ShrImmSaturatingNarrow_V_2D2S_2D4S([ValueSource("_ShrImmSaturatingNarrow_V_2D2S_2D4S_")] uint opcodes,
|
||||
public void ShrImmSaturatingNarrow_V_2D2S_2D4S([ValueSource(nameof(_ShrImmSaturatingNarrow_V_2D2S_2D4S_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 0u)] uint rn,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
|
||||
[Values(1u, 32u)] [Random(2u, 31u, RndCntShift)] uint shift,
|
||||
[ValueSource(nameof(_1D_))] ulong z,
|
||||
[ValueSource(nameof(_1D_))] ulong a,
|
||||
[Values(1u, 32u)] uint shift,
|
||||
[Values(0b0u, 0b1u)] uint q) // <2D2S, 2D4S>
|
||||
{
|
||||
uint immHb = (64 - shift) & 0x7F;
|
||||
@ -1114,4 +1108,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -13,33 +13,30 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Types)"
|
||||
private static ulong[] _1D_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _2S_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
|
||||
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul, 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _4H_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
|
||||
0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul, 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _8B_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, 0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
#endregion
|
||||
|
||||
#region "ValueSource (Opcodes)"
|
||||
private static uint[] _Vshr_Imm_SU8_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xf2880010u, // VSHR.S8 D0, D0, #8
|
||||
0xf2880110u, // VSRA.S8 D0, D0, #8
|
||||
@ -50,7 +47,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Vshr_Imm_SU16_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xf2900010u, // VSHR.S16 D0, D0, #16
|
||||
0xf2900110u, // VSRA.S16 D0, D0, #16
|
||||
@ -61,7 +58,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Vshr_Imm_SU32_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xf2a00010u, // VSHR.S32 D0, D0, #32
|
||||
0xf2a00110u, // VSRA.S32 D0, D0, #32
|
||||
@ -72,7 +69,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Vshr_Imm_SU64_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xf2800190u, // VSRA.S64 D0, D0, #64
|
||||
0xf2800290u, // VRSHR.S64 D0, D0, #64
|
||||
@ -82,7 +79,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Vqshrn_Vqrshrn_Vrshrn_Imm_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xf2800910u, // VORR.I16 D0, #0 (immediate value changes it into QSHRN)
|
||||
0xf2800950u, // VORR.I16 Q0, #0 (immediate value changes it into QRSHRN)
|
||||
@ -92,7 +89,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _Vqshrun_Vqrshrun_Imm_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xf3800810u, // VMOV.I16 D0, #0x80 (immediate value changes it into QSHRUN)
|
||||
0xf3800850u // VMOV.I16 Q0, #0x80 (immediate value changes it into QRSHRUN)
|
||||
@ -104,12 +101,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
private const int RndCntShiftImm = 2;
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Vshr_Imm_SU8([ValueSource("_Vshr_Imm_SU8_")] uint opcode,
|
||||
public void Vshr_Imm_SU8([ValueSource(nameof(_Vshr_Imm_SU8_))] uint opcode,
|
||||
[Range(0u, 3u)] uint rd,
|
||||
[Range(0u, 3u)] uint rm,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_8B_")] [Random(RndCnt)] ulong b,
|
||||
[Values(1u, 8u)] [Random(2u, 7u, RndCntShiftImm)] uint shiftImm,
|
||||
[ValueSource(nameof(_8B_))] ulong z,
|
||||
[ValueSource(nameof(_8B_))] ulong b,
|
||||
[Values(1u, 8u)] uint shiftImm,
|
||||
[Values] bool u,
|
||||
[Values] bool q)
|
||||
{
|
||||
@ -119,12 +116,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Vshr_Imm_SU16([ValueSource("_Vshr_Imm_SU16_")] uint opcode,
|
||||
public void Vshr_Imm_SU16([ValueSource(nameof(_Vshr_Imm_SU16_))] uint opcode,
|
||||
[Range(0u, 3u)] uint rd,
|
||||
[Range(0u, 3u)] uint rm,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_4H_")] [Random(RndCnt)] ulong b,
|
||||
[Values(1u, 16u)] [Random(2u, 15u, RndCntShiftImm)] uint shiftImm,
|
||||
[ValueSource(nameof(_4H_))] ulong z,
|
||||
[ValueSource(nameof(_4H_))] ulong b,
|
||||
[Values(1u, 16u)] uint shiftImm,
|
||||
[Values] bool u,
|
||||
[Values] bool q)
|
||||
{
|
||||
@ -134,12 +131,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Vshr_Imm_SU32([ValueSource("_Vshr_Imm_SU32_")] uint opcode,
|
||||
public void Vshr_Imm_SU32([ValueSource(nameof(_Vshr_Imm_SU32_))] uint opcode,
|
||||
[Range(0u, 3u)] uint rd,
|
||||
[Range(0u, 3u)] uint rm,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_2S_")] [Random(RndCnt)] ulong b,
|
||||
[Values(1u, 32u)] [Random(2u, 31u, RndCntShiftImm)] uint shiftImm,
|
||||
[ValueSource(nameof(_2S_))] ulong z,
|
||||
[ValueSource(nameof(_2S_))] ulong b,
|
||||
[Values(1u, 32u)] uint shiftImm,
|
||||
[Values] bool u,
|
||||
[Values] bool q)
|
||||
{
|
||||
@ -149,12 +146,12 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Vshr_Imm_SU64([ValueSource("_Vshr_Imm_SU64_")] uint opcode,
|
||||
public void Vshr_Imm_SU64([ValueSource(nameof(_Vshr_Imm_SU64_))] uint opcode,
|
||||
[Range(0u, 3u)] uint rd,
|
||||
[Range(0u, 3u)] uint rm,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
|
||||
[ValueSource("_1D_")] [Random(RndCnt)] ulong b,
|
||||
[Values(1u, 64u)] [Random(2u, 63u, RndCntShiftImm)] uint shiftImm,
|
||||
[ValueSource(nameof(_1D_))] ulong z,
|
||||
[ValueSource(nameof(_1D_))] ulong b,
|
||||
[Values(1u, 64u)] uint shiftImm,
|
||||
[Values] bool u,
|
||||
[Values] bool q)
|
||||
{
|
||||
@ -195,7 +192,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Vshl_Imm([Values(0u)] uint rd,
|
||||
[Values(2u, 0u)] uint rm,
|
||||
[Values(0u, 1u, 2u, 3u)] uint size,
|
||||
[Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
|
||||
[Random(RndCntShiftImm)] uint shiftImm,
|
||||
[Random(RndCnt)] ulong z,
|
||||
[Random(RndCnt)] ulong a,
|
||||
[Random(RndCnt)] ulong b,
|
||||
@ -229,7 +226,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
public void Vshrn_Imm([Values(0u, 1u)] uint rd,
|
||||
[Values(2u, 0u)] uint rm,
|
||||
[Values(0u, 1u, 2u)] uint size,
|
||||
[Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
|
||||
[Random(RndCntShiftImm)] uint shiftImm,
|
||||
[Random(RndCnt)] ulong z,
|
||||
[Random(RndCnt)] ulong a,
|
||||
[Random(RndCnt)] ulong b)
|
||||
@ -253,11 +250,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Vqshrn_Vqrshrn_Vrshrn_Imm([ValueSource("_Vqshrn_Vqrshrn_Vrshrn_Imm_")] uint opcode,
|
||||
public void Vqshrn_Vqrshrn_Vrshrn_Imm([ValueSource(nameof(_Vqshrn_Vqrshrn_Vrshrn_Imm_))] uint opcode,
|
||||
[Values(0u, 1u)] uint rd,
|
||||
[Values(2u, 0u)] uint rm,
|
||||
[Values(0u, 1u, 2u)] uint size,
|
||||
[Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
|
||||
[Random(RndCntShiftImm)] uint shiftImm,
|
||||
[Random(RndCnt)] ulong z,
|
||||
[Random(RndCnt)] ulong a,
|
||||
[Random(RndCnt)] ulong b,
|
||||
@ -287,11 +284,11 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Vqshrun_Vqrshrun_Imm([ValueSource("_Vqshrun_Vqrshrun_Imm_")] uint opcode,
|
||||
public void Vqshrun_Vqrshrun_Imm([ValueSource(nameof(_Vqshrun_Vqrshrun_Imm_))] uint opcode,
|
||||
[Values(0u, 1u)] uint rd,
|
||||
[Values(2u, 0u)] uint rm,
|
||||
[Values(0u, 1u, 2u)] uint size,
|
||||
[Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
|
||||
[Random(RndCntShiftImm)] uint shiftImm,
|
||||
[Random(RndCnt)] ulong z,
|
||||
[Random(RndCnt)] ulong a,
|
||||
[Random(RndCnt)] ulong b)
|
||||
@ -315,4 +312,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,9 +1,7 @@
|
||||
#define SimdTbl
|
||||
|
||||
using ARMeilleure.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
using System.Collections.Generic;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
@ -16,17 +14,17 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "Helper methods"
|
||||
private static ulong GenIdxsForTbls(int regs)
|
||||
{
|
||||
const byte idxInRngMin = (byte)0;
|
||||
byte idxInRngMax = (byte)((16 * regs) - 1);
|
||||
byte idxOutRngMin = (byte) (16 * regs);
|
||||
const byte idxOutRngMax = (byte)255;
|
||||
const byte idxInRngMin = 0;
|
||||
byte idxInRngMax = (byte)((16 * regs) - 1);
|
||||
byte idxOutRngMin = (byte) (16 * regs);
|
||||
const byte idxOutRngMax = 255;
|
||||
|
||||
ulong idxs = 0ul;
|
||||
|
||||
for (int cnt = 1; cnt <= 8; cnt++)
|
||||
{
|
||||
ulong idxInRng = (ulong)TestContext.CurrentContext.Random.NextByte(idxInRngMin, idxInRngMax);
|
||||
ulong idxOutRng = (ulong)TestContext.CurrentContext.Random.NextByte(idxOutRngMin, idxOutRngMax);
|
||||
ulong idxInRng = TestContext.CurrentContext.Random.NextByte(idxInRngMin, idxInRngMax);
|
||||
ulong idxOutRng = TestContext.CurrentContext.Random.NextByte(idxOutRngMin, idxOutRngMax);
|
||||
|
||||
ulong idx = TestContext.CurrentContext.Random.NextBool() ? idxInRng : idxOutRng;
|
||||
|
||||
@ -40,8 +38,8 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Types)"
|
||||
private static ulong[] _8B_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
|
||||
0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static IEnumerable<ulong> _GenIdxsForTbl1_()
|
||||
@ -100,7 +98,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Opcodes)"
|
||||
private static uint[] _SingleRegisterTable_V_8B_16B_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0E000000u, // TBL V0.8B, { V0.16B }, V0.8B
|
||||
0x0E001000u // TBX V0.8B, { V0.16B }, V0.8B
|
||||
@ -109,7 +107,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _TwoRegisterTable_V_8B_16B_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0E002000u, // TBL V0.8B, { V0.16B, V1.16B }, V0.8B
|
||||
0x0E003000u // TBX V0.8B, { V0.16B, V1.16B }, V0.8B
|
||||
@ -118,7 +116,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _ThreeRegisterTable_V_8B_16B_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0E004000u, // TBL V0.8B, { V0.16B, V1.16B, V2.16B }, V0.8B
|
||||
0x0E005000u // TBX V0.8B, { V0.16B, V1.16B, V2.16B }, V0.8B
|
||||
@ -127,7 +125,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
|
||||
private static uint[] _FourRegisterTable_V_8B_16B_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0x0E006000u, // TBL V0.8B, { V0.16B, V1.16B, V2.16B, V3.16B }, V0.8B
|
||||
0x0E006000u // TBX V0.8B, { V0.16B, V1.16B, V2.16B, V3.16B }, V0.8B
|
||||
@ -135,18 +133,16 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endregion
|
||||
|
||||
private const int RndCntDest = 2;
|
||||
private const int RndCntTbls = 2;
|
||||
private const int RndCntIdxs = 2;
|
||||
|
||||
[Test, Pairwise]
|
||||
public void SingleRegisterTable_V_8B_16B([ValueSource("_SingleRegisterTable_V_8B_16B_")] uint opcodes,
|
||||
public void SingleRegisterTable_V_8B_16B([ValueSource(nameof(_SingleRegisterTable_V_8B_16B_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[Values(2u)] uint rm,
|
||||
[ValueSource("_8B_")] [Random(RndCntDest)] ulong z,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table0,
|
||||
[ValueSource("_GenIdxsForTbl1_")] ulong indexes,
|
||||
[ValueSource(nameof(_8B_))] ulong z,
|
||||
[ValueSource(nameof(_8B_))] ulong table0,
|
||||
[ValueSource(nameof(_GenIdxsForTbl1_))] ulong indexes,
|
||||
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
|
||||
{
|
||||
opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -162,14 +158,14 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void TwoRegisterTable_V_8B_16B([ValueSource("_TwoRegisterTable_V_8B_16B_")] uint opcodes,
|
||||
public void TwoRegisterTable_V_8B_16B([ValueSource(nameof(_TwoRegisterTable_V_8B_16B_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[Values(3u)] uint rm,
|
||||
[ValueSource("_8B_")] [Random(RndCntDest)] ulong z,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table0,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table1,
|
||||
[ValueSource("_GenIdxsForTbl2_")] ulong indexes,
|
||||
[ValueSource(nameof(_8B_))] ulong z,
|
||||
[ValueSource(nameof(_8B_))] ulong table0,
|
||||
[ValueSource(nameof(_8B_))] ulong table1,
|
||||
[ValueSource(nameof(_GenIdxsForTbl2_))] ulong indexes,
|
||||
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
|
||||
{
|
||||
opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -186,14 +182,14 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Mod_TwoRegisterTable_V_8B_16B([ValueSource("_TwoRegisterTable_V_8B_16B_")] uint opcodes,
|
||||
public void Mod_TwoRegisterTable_V_8B_16B([ValueSource(nameof(_TwoRegisterTable_V_8B_16B_))] uint opcodes,
|
||||
[Values(30u, 1u)] uint rd,
|
||||
[Values(31u)] uint rn,
|
||||
[Values(1u, 30u)] uint rm,
|
||||
[ValueSource("_8B_")] [Random(RndCntDest)] ulong z,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table0,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table1,
|
||||
[ValueSource("_GenIdxsForTbl2_")] ulong indexes,
|
||||
[ValueSource(nameof(_8B_))] ulong z,
|
||||
[ValueSource(nameof(_8B_))] ulong table0,
|
||||
[ValueSource(nameof(_8B_))] ulong table1,
|
||||
[ValueSource(nameof(_GenIdxsForTbl2_))] ulong indexes,
|
||||
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
|
||||
{
|
||||
opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -210,15 +206,15 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void ThreeRegisterTable_V_8B_16B([ValueSource("_ThreeRegisterTable_V_8B_16B_")] uint opcodes,
|
||||
public void ThreeRegisterTable_V_8B_16B([ValueSource(nameof(_ThreeRegisterTable_V_8B_16B_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[Values(4u)] uint rm,
|
||||
[ValueSource("_8B_")] [Random(RndCntDest)] ulong z,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table0,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table1,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table2,
|
||||
[ValueSource("_GenIdxsForTbl3_")] ulong indexes,
|
||||
[ValueSource(nameof(_8B_))] ulong z,
|
||||
[ValueSource(nameof(_8B_))] ulong table0,
|
||||
[ValueSource(nameof(_8B_))] ulong table1,
|
||||
[ValueSource(nameof(_8B_))] ulong table2,
|
||||
[ValueSource(nameof(_GenIdxsForTbl3_))] ulong indexes,
|
||||
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
|
||||
{
|
||||
opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -236,15 +232,15 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Mod_ThreeRegisterTable_V_8B_16B([ValueSource("_ThreeRegisterTable_V_8B_16B_")] uint opcodes,
|
||||
public void Mod_ThreeRegisterTable_V_8B_16B([ValueSource(nameof(_ThreeRegisterTable_V_8B_16B_))] uint opcodes,
|
||||
[Values(30u, 2u)] uint rd,
|
||||
[Values(31u)] uint rn,
|
||||
[Values(2u, 30u)] uint rm,
|
||||
[ValueSource("_8B_")] [Random(RndCntDest)] ulong z,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table0,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table1,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table2,
|
||||
[ValueSource("_GenIdxsForTbl3_")] ulong indexes,
|
||||
[ValueSource(nameof(_8B_))] ulong z,
|
||||
[ValueSource(nameof(_8B_))] ulong table0,
|
||||
[ValueSource(nameof(_8B_))] ulong table1,
|
||||
[ValueSource(nameof(_8B_))] ulong table2,
|
||||
[ValueSource(nameof(_GenIdxsForTbl3_))] ulong indexes,
|
||||
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
|
||||
{
|
||||
opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -262,16 +258,16 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void FourRegisterTable_V_8B_16B([ValueSource("_FourRegisterTable_V_8B_16B_")] uint opcodes,
|
||||
public void FourRegisterTable_V_8B_16B([ValueSource(nameof(_FourRegisterTable_V_8B_16B_))] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u)] uint rn,
|
||||
[Values(5u)] uint rm,
|
||||
[ValueSource("_8B_")] [Random(RndCntDest)] ulong z,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table0,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table1,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table2,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table3,
|
||||
[ValueSource("_GenIdxsForTbl4_")] ulong indexes,
|
||||
[ValueSource(nameof(_8B_))] ulong z,
|
||||
[ValueSource(nameof(_8B_))] ulong table0,
|
||||
[ValueSource(nameof(_8B_))] ulong table1,
|
||||
[ValueSource(nameof(_8B_))] ulong table2,
|
||||
[ValueSource(nameof(_8B_))] ulong table3,
|
||||
[ValueSource(nameof(_GenIdxsForTbl4_))] ulong indexes,
|
||||
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
|
||||
{
|
||||
opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -290,16 +286,16 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
[Test, Pairwise]
|
||||
public void Mod_FourRegisterTable_V_8B_16B([ValueSource("_FourRegisterTable_V_8B_16B_")] uint opcodes,
|
||||
public void Mod_FourRegisterTable_V_8B_16B([ValueSource(nameof(_FourRegisterTable_V_8B_16B_))] uint opcodes,
|
||||
[Values(30u, 3u)] uint rd,
|
||||
[Values(31u)] uint rn,
|
||||
[Values(3u, 30u)] uint rm,
|
||||
[ValueSource("_8B_")] [Random(RndCntDest)] ulong z,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table0,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table1,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table2,
|
||||
[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table3,
|
||||
[ValueSource("_GenIdxsForTbl4_")] ulong indexes,
|
||||
[ValueSource(nameof(_8B_))] ulong z,
|
||||
[ValueSource(nameof(_8B_))] ulong table0,
|
||||
[ValueSource(nameof(_8B_))] ulong table1,
|
||||
[ValueSource(nameof(_8B_))] ulong table2,
|
||||
[ValueSource(nameof(_8B_))] ulong table3,
|
||||
[ValueSource(nameof(_GenIdxsForTbl4_))] ulong indexes,
|
||||
[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
|
||||
{
|
||||
opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
@ -318,4 +314,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,9 +1,7 @@
|
||||
#define System
|
||||
|
||||
using ARMeilleure.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
using System.Collections.Generic;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
@ -40,7 +38,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
#region "ValueSource (Opcodes)"
|
||||
private static uint[] _MrsMsr_Nzcv_()
|
||||
{
|
||||
return new uint[]
|
||||
return new[]
|
||||
{
|
||||
0xD53B4200u, // MRS X0, NZCV
|
||||
0xD51B4200u // MSR NZCV, X0
|
||||
@ -48,12 +46,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endregion
|
||||
|
||||
private const int RndCnt = 2;
|
||||
|
||||
[Test, Pairwise]
|
||||
public void MrsMsr_Nzcv([ValueSource("_MrsMsr_Nzcv_")] uint opcodes,
|
||||
[Values(0u, 1u, 31u)] uint rt,
|
||||
[ValueSource("_GenNzcv_")] [Random(RndCnt)] ulong xt)
|
||||
[ValueSource("_GenNzcv_")] ulong xt)
|
||||
{
|
||||
opcodes |= (rt & 31) << 0;
|
||||
|
||||
@ -70,4 +66,4 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -142,10 +142,10 @@ namespace Ryujinx.Tests.Cpu
|
||||
Assert.That(GetContext().GetX(1), Is.EqualTo(w1 ^ w2));
|
||||
break;
|
||||
case 2:
|
||||
Assert.That(GetContext().GetX(1), Is.EqualTo(shift >= 32 ? 0 : (uint)(w1 << (int)shift)));
|
||||
Assert.That(GetContext().GetX(1), Is.EqualTo(shift >= 32 ? 0 : w1 << (int)shift));
|
||||
break;
|
||||
case 3:
|
||||
Assert.That(GetContext().GetX(1), Is.EqualTo(shift >= 32 ? 0 : (uint)(w1 >> (int)shift)));
|
||||
Assert.That(GetContext().GetX(1), Is.EqualTo(shift >= 32 ? 0 : w1 >> (int)shift));
|
||||
break;
|
||||
case 4:
|
||||
Assert.That(GetContext().GetX(1), Is.EqualTo(shift >= 32 ? (uint)((int)w1 >> 31) : (uint)((int)w1 >> (int)shift)));
|
||||
|
||||
Reference in New Issue
Block a user