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Replace unicorn bindings with Nuget package (#4378)

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* Replace unicorn bindings with Nuget package

* Use nameof for ValueSource args

* Remove redundant code from test projects

* Fix wrong values for EmuStart()

Add notes to address this later again

* Improve formatting

* Fix formatting/alignment issues
This commit is contained in:
TSRBerry
2023-02-09 02:24:32 +01:00
committed by GitHub
parent b3f0978869
commit ec8d4f3af5
64 changed files with 2276 additions and 3576 deletions
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29
Ryujinx.Tests/Cpu/CpuTestMisc.cs
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@ -1,9 +1,7 @@
#define Misc
using ARMeilleure.State;
using NUnit.Framework;
using System;
using System.Collections.Generic;
@ -59,7 +57,6 @@ namespace Ryujinx.Tests.Cpu
#endregion
private const int RndCnt = 2;
private const int RndCntImm = 2;
private static readonly bool NoZeros = false;
private static readonly bool NoInfs = false;
@ -68,8 +65,8 @@ namespace Ryujinx.Tests.Cpu
#region "AluImm & Csel"
[Test, Pairwise]
public void Adds_Csinc_64bit([Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0u, 4095u)] uint imm,
[Values(0b00u, 0b01u)] uint shift, // <LSL #0, LSL #12>
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
@ -93,8 +90,8 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise]
public void Adds_Csinc_32bit([Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0u, 4095u)] uint imm,
[Values(0b00u, 0b01u)] uint shift, // <LSL #0, LSL #12>
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
@ -118,8 +115,8 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise]
public void Subs_Csinc_64bit([Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
[Values(0u, 4095u)] uint imm,
[Values(0b00u, 0b01u)] uint shift, // <LSL #0, LSL #12>
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
@ -143,8 +140,8 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise]
public void Subs_Csinc_32bit([Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
0x80000000u, 0xFFFFFFFFu)] uint wn,
[Values(0u, 4095u)] uint imm,
[Values(0b00u, 0b01u)] uint shift, // <LSL #0, LSL #12>
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
@ -412,9 +409,9 @@ namespace Ryujinx.Tests.Cpu
[Explicit]
[Test, Pairwise]
public void Misc4([ValueSource("_1S_F_")] ulong a,
[ValueSource("_1S_F_")] ulong b,
[ValueSource("_1S_F_")] ulong c,
public void Misc4([ValueSource(nameof(_1S_F_))] ulong a,
[ValueSource(nameof(_1S_F_))] ulong b,
[ValueSource(nameof(_1S_F_))] ulong c,
[Values(0ul, 1ul, 2ul, 3ul)] ulong displacement)
{
if (!BitConverter.IsLittleEndian)
@ -460,7 +457,7 @@ namespace Ryujinx.Tests.Cpu
[Explicit]
[Test]
public void Misc5([ValueSource("_1S_F_")] ulong a)
public void Misc5([ValueSource(nameof(_1S_F_))] ulong a)
{
SetContext(
v0: MakeVectorE0E1(a, TestContext.CurrentContext.Random.NextULong()),
@ -482,4 +479,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
}
}