mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2025-06-28 13:50:46 -07:00
Replace unicorn bindings with Nuget package (#4378)
* Replace unicorn bindings with Nuget package * Use nameof for ValueSource args * Remove redundant code from test projects * Fix wrong values for EmuStart() Add notes to address this later again * Improve formatting * Fix formatting/alignment issues
This commit is contained in:
TSRBerry
GitHub
@ -1,11 +1,14 @@
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using System;
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namespace Ryujinx.Tests.Unicorn
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{
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[Flags]
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public enum MemoryPermission
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{
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NONE = 0,
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READ = 1,
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WRITE = 2,
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EXEC = 4,
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ALL = 7,
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None = 0,
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Read = 1,
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Write = 2,
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Exec = 4,
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All = 7,
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}
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}
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}
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@ -1,20 +0,0 @@
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// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
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// ReSharper disable InconsistentNaming
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namespace Ryujinx.Tests.Unicorn.Native.Const
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{
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public enum Arch
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{
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ARM = 1,
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ARM64 = 2,
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MIPS = 3,
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X86 = 4,
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PPC = 5,
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SPARC = 6,
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M68K = 7,
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RISCV = 8,
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S390X = 9,
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TRICORE = 10,
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MAX = 11,
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}
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}
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@ -1,200 +0,0 @@
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// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
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// ReSharper disable InconsistentNaming
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namespace Ryujinx.Tests.Unicorn.Native.Const
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{
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public enum Arm
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{
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// ARM CPU
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CPU_ARM_926 = 0,
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CPU_ARM_946 = 1,
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CPU_ARM_1026 = 2,
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CPU_ARM_1136_R2 = 3,
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CPU_ARM_1136 = 4,
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CPU_ARM_1176 = 5,
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CPU_ARM_11MPCORE = 6,
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CPU_ARM_CORTEX_M0 = 7,
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CPU_ARM_CORTEX_M3 = 8,
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CPU_ARM_CORTEX_M4 = 9,
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CPU_ARM_CORTEX_M7 = 10,
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CPU_ARM_CORTEX_M33 = 11,
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CPU_ARM_CORTEX_R5 = 12,
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CPU_ARM_CORTEX_R5F = 13,
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CPU_ARM_CORTEX_A7 = 14,
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CPU_ARM_CORTEX_A8 = 15,
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CPU_ARM_CORTEX_A9 = 16,
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CPU_ARM_CORTEX_A15 = 17,
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CPU_ARM_TI925T = 18,
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CPU_ARM_SA1100 = 19,
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CPU_ARM_SA1110 = 20,
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CPU_ARM_PXA250 = 21,
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CPU_ARM_PXA255 = 22,
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CPU_ARM_PXA260 = 23,
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CPU_ARM_PXA261 = 24,
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CPU_ARM_PXA262 = 25,
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CPU_ARM_PXA270 = 26,
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CPU_ARM_PXA270A0 = 27,
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CPU_ARM_PXA270A1 = 28,
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CPU_ARM_PXA270B0 = 29,
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CPU_ARM_PXA270B1 = 30,
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CPU_ARM_PXA270C0 = 31,
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CPU_ARM_PXA270C5 = 32,
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CPU_ARM_MAX = 33,
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CPU_ARM_ENDING = 34,
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// ARM registers
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REG_INVALID = 0,
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REG_APSR = 1,
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REG_APSR_NZCV = 2,
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REG_CPSR = 3,
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REG_FPEXC = 4,
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REG_FPINST = 5,
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REG_FPSCR = 6,
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REG_FPSCR_NZCV = 7,
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REG_FPSID = 8,
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REG_ITSTATE = 9,
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REG_LR = 10,
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REG_PC = 11,
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REG_SP = 12,
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REG_SPSR = 13,
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REG_D0 = 14,
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REG_D1 = 15,
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REG_D2 = 16,
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REG_D3 = 17,
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REG_D4 = 18,
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REG_D5 = 19,
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REG_D6 = 20,
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REG_D7 = 21,
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REG_D8 = 22,
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REG_D9 = 23,
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REG_D10 = 24,
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REG_D11 = 25,
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REG_D12 = 26,
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REG_D13 = 27,
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REG_D14 = 28,
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REG_D15 = 29,
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REG_D16 = 30,
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REG_D17 = 31,
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REG_D18 = 32,
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REG_D19 = 33,
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REG_D20 = 34,
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REG_D21 = 35,
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REG_D22 = 36,
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REG_D23 = 37,
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REG_D24 = 38,
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REG_D25 = 39,
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REG_D26 = 40,
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REG_D27 = 41,
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REG_D28 = 42,
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REG_D29 = 43,
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REG_D30 = 44,
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REG_D31 = 45,
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REG_FPINST2 = 46,
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REG_MVFR0 = 47,
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REG_MVFR1 = 48,
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REG_MVFR2 = 49,
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REG_Q0 = 50,
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REG_Q1 = 51,
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REG_Q2 = 52,
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REG_Q3 = 53,
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REG_Q4 = 54,
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REG_Q5 = 55,
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REG_Q6 = 56,
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REG_Q7 = 57,
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REG_Q8 = 58,
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REG_Q9 = 59,
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REG_Q10 = 60,
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REG_Q11 = 61,
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REG_Q12 = 62,
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REG_Q13 = 63,
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REG_Q14 = 64,
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REG_Q15 = 65,
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REG_R0 = 66,
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REG_R1 = 67,
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REG_R2 = 68,
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REG_R3 = 69,
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REG_R4 = 70,
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REG_R5 = 71,
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REG_R6 = 72,
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REG_R7 = 73,
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REG_R8 = 74,
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REG_R9 = 75,
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REG_R10 = 76,
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REG_R11 = 77,
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REG_R12 = 78,
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REG_S0 = 79,
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REG_S1 = 80,
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REG_S2 = 81,
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REG_S3 = 82,
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REG_S4 = 83,
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REG_S5 = 84,
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REG_S6 = 85,
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REG_S7 = 86,
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REG_S8 = 87,
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REG_S9 = 88,
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REG_S10 = 89,
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REG_S11 = 90,
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REG_S12 = 91,
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REG_S13 = 92,
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REG_S14 = 93,
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REG_S15 = 94,
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REG_S16 = 95,
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REG_S17 = 96,
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REG_S18 = 97,
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REG_S19 = 98,
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REG_S20 = 99,
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REG_S21 = 100,
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REG_S22 = 101,
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REG_S23 = 102,
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REG_S24 = 103,
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REG_S25 = 104,
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REG_S26 = 105,
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REG_S27 = 106,
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REG_S28 = 107,
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REG_S29 = 108,
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REG_S30 = 109,
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REG_S31 = 110,
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REG_C1_C0_2 = 111,
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REG_C13_C0_2 = 112,
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REG_C13_C0_3 = 113,
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REG_IPSR = 114,
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REG_MSP = 115,
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REG_PSP = 116,
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REG_CONTROL = 117,
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REG_IAPSR = 118,
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REG_EAPSR = 119,
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REG_XPSR = 120,
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REG_EPSR = 121,
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REG_IEPSR = 122,
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REG_PRIMASK = 123,
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REG_BASEPRI = 124,
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REG_BASEPRI_MAX = 125,
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REG_FAULTMASK = 126,
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REG_APSR_NZCVQ = 127,
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REG_APSR_G = 128,
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REG_APSR_NZCVQG = 129,
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REG_IAPSR_NZCVQ = 130,
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REG_IAPSR_G = 131,
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REG_IAPSR_NZCVQG = 132,
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REG_EAPSR_NZCVQ = 133,
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REG_EAPSR_G = 134,
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REG_EAPSR_NZCVQG = 135,
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REG_XPSR_NZCVQ = 136,
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REG_XPSR_G = 137,
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REG_XPSR_NZCVQG = 138,
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REG_CP_REG = 139,
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REG_ENDING = 140,
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// alias registers
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REG_R13 = 12,
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REG_R14 = 10,
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REG_R15 = 11,
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REG_SB = 75,
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REG_SL = 76,
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REG_FP = 77,
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REG_IP = 78,
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}
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}
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@ -1,341 +0,0 @@
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// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
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// ReSharper disable InconsistentNaming
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namespace Ryujinx.Tests.Unicorn.Native.Const
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{
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public enum Arm64
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{
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// ARM64 CPU
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CPU_ARM64_A57 = 0,
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CPU_ARM64_A53 = 1,
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CPU_ARM64_A72 = 2,
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CPU_ARM64_MAX = 3,
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CPU_ARM64_ENDING = 4,
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// ARM64 registers
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REG_INVALID = 0,
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REG_X29 = 1,
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REG_X30 = 2,
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REG_NZCV = 3,
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REG_SP = 4,
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REG_WSP = 5,
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REG_WZR = 6,
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REG_XZR = 7,
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REG_B0 = 8,
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REG_B1 = 9,
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REG_B2 = 10,
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REG_B3 = 11,
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REG_B4 = 12,
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REG_B5 = 13,
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REG_B6 = 14,
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REG_B7 = 15,
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REG_B8 = 16,
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REG_B9 = 17,
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REG_B10 = 18,
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REG_B11 = 19,
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REG_B12 = 20,
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REG_B13 = 21,
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REG_B14 = 22,
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REG_B15 = 23,
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REG_B16 = 24,
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REG_B17 = 25,
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REG_B18 = 26,
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REG_B19 = 27,
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REG_B20 = 28,
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REG_B21 = 29,
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REG_B22 = 30,
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REG_B23 = 31,
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REG_B24 = 32,
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REG_B25 = 33,
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REG_B26 = 34,
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REG_B27 = 35,
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REG_B28 = 36,
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REG_B29 = 37,
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REG_B30 = 38,
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REG_B31 = 39,
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REG_D0 = 40,
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REG_D1 = 41,
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REG_D2 = 42,
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REG_D3 = 43,
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REG_D4 = 44,
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REG_D5 = 45,
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REG_D6 = 46,
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REG_D7 = 47,
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REG_D8 = 48,
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REG_D9 = 49,
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REG_D10 = 50,
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REG_D11 = 51,
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REG_D12 = 52,
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REG_D13 = 53,
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REG_D14 = 54,
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REG_D15 = 55,
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REG_D16 = 56,
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REG_D17 = 57,
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REG_D18 = 58,
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REG_D19 = 59,
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REG_D20 = 60,
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REG_D21 = 61,
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REG_D22 = 62,
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REG_D23 = 63,
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REG_D24 = 64,
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REG_D25 = 65,
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REG_D26 = 66,
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REG_D27 = 67,
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REG_D28 = 68,
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REG_D29 = 69,
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REG_D30 = 70,
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REG_D31 = 71,
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REG_H0 = 72,
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REG_H1 = 73,
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REG_H2 = 74,
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REG_H3 = 75,
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REG_H4 = 76,
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REG_H5 = 77,
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REG_H6 = 78,
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REG_H7 = 79,
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REG_H8 = 80,
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REG_H9 = 81,
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REG_H10 = 82,
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REG_H11 = 83,
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REG_H12 = 84,
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REG_H13 = 85,
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REG_H14 = 86,
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REG_H15 = 87,
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REG_H16 = 88,
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REG_H17 = 89,
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REG_H18 = 90,
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REG_H19 = 91,
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REG_H20 = 92,
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REG_H21 = 93,
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REG_H22 = 94,
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REG_H23 = 95,
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REG_H24 = 96,
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REG_H25 = 97,
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REG_H26 = 98,
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REG_H27 = 99,
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REG_H28 = 100,
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REG_H29 = 101,
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REG_H30 = 102,
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REG_H31 = 103,
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REG_Q0 = 104,
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REG_Q1 = 105,
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REG_Q2 = 106,
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REG_Q3 = 107,
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REG_Q4 = 108,
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REG_Q5 = 109,
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REG_Q6 = 110,
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REG_Q7 = 111,
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REG_Q8 = 112,
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REG_Q9 = 113,
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REG_Q10 = 114,
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REG_Q11 = 115,
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REG_Q12 = 116,
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REG_Q13 = 117,
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REG_Q14 = 118,
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REG_Q15 = 119,
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REG_Q16 = 120,
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REG_Q17 = 121,
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REG_Q18 = 122,
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REG_Q19 = 123,
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REG_Q20 = 124,
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REG_Q21 = 125,
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REG_Q22 = 126,
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REG_Q23 = 127,
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REG_Q24 = 128,
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REG_Q25 = 129,
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REG_Q26 = 130,
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REG_Q27 = 131,
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REG_Q28 = 132,
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REG_Q29 = 133,
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REG_Q30 = 134,
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REG_Q31 = 135,
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REG_S0 = 136,
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REG_S1 = 137,
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REG_S2 = 138,
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REG_S3 = 139,
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REG_S4 = 140,
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REG_S5 = 141,
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REG_S6 = 142,
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REG_S7 = 143,
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REG_S8 = 144,
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REG_S9 = 145,
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REG_S10 = 146,
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REG_S11 = 147,
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REG_S12 = 148,
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REG_S13 = 149,
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REG_S14 = 150,
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REG_S15 = 151,
|
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REG_S16 = 152,
|
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REG_S17 = 153,
|
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REG_S18 = 154,
|
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REG_S19 = 155,
|
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REG_S20 = 156,
|
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REG_S21 = 157,
|
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REG_S22 = 158,
|
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REG_S23 = 159,
|
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REG_S24 = 160,
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REG_S25 = 161,
|
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REG_S26 = 162,
|
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REG_S27 = 163,
|
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REG_S28 = 164,
|
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REG_S29 = 165,
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REG_S30 = 166,
|
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REG_S31 = 167,
|
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REG_W0 = 168,
|
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REG_W1 = 169,
|
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REG_W2 = 170,
|
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REG_W3 = 171,
|
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REG_W4 = 172,
|
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REG_W5 = 173,
|
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REG_W6 = 174,
|
||||
REG_W7 = 175,
|
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REG_W8 = 176,
|
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REG_W9 = 177,
|
||||
REG_W10 = 178,
|
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REG_W11 = 179,
|
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REG_W12 = 180,
|
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REG_W13 = 181,
|
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REG_W14 = 182,
|
||||
REG_W15 = 183,
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REG_W16 = 184,
|
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REG_W17 = 185,
|
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REG_W18 = 186,
|
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REG_W19 = 187,
|
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REG_W20 = 188,
|
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REG_W21 = 189,
|
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REG_W22 = 190,
|
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REG_W23 = 191,
|
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REG_W24 = 192,
|
||||
REG_W25 = 193,
|
||||
REG_W26 = 194,
|
||||
REG_W27 = 195,
|
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REG_W28 = 196,
|
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REG_W29 = 197,
|
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REG_W30 = 198,
|
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REG_X0 = 199,
|
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REG_X1 = 200,
|
||||
REG_X2 = 201,
|
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REG_X3 = 202,
|
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REG_X4 = 203,
|
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REG_X5 = 204,
|
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REG_X6 = 205,
|
||||
REG_X7 = 206,
|
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REG_X8 = 207,
|
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REG_X9 = 208,
|
||||
REG_X10 = 209,
|
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REG_X11 = 210,
|
||||
REG_X12 = 211,
|
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REG_X13 = 212,
|
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REG_X14 = 213,
|
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REG_X15 = 214,
|
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REG_X16 = 215,
|
||||
REG_X17 = 216,
|
||||
REG_X18 = 217,
|
||||
REG_X19 = 218,
|
||||
REG_X20 = 219,
|
||||
REG_X21 = 220,
|
||||
REG_X22 = 221,
|
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REG_X23 = 222,
|
||||
REG_X24 = 223,
|
||||
REG_X25 = 224,
|
||||
REG_X26 = 225,
|
||||
REG_X27 = 226,
|
||||
REG_X28 = 227,
|
||||
REG_V0 = 228,
|
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REG_V1 = 229,
|
||||
REG_V2 = 230,
|
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REG_V3 = 231,
|
||||
REG_V4 = 232,
|
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REG_V5 = 233,
|
||||
REG_V6 = 234,
|
||||
REG_V7 = 235,
|
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REG_V8 = 236,
|
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REG_V9 = 237,
|
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REG_V10 = 238,
|
||||
REG_V11 = 239,
|
||||
REG_V12 = 240,
|
||||
REG_V13 = 241,
|
||||
REG_V14 = 242,
|
||||
REG_V15 = 243,
|
||||
REG_V16 = 244,
|
||||
REG_V17 = 245,
|
||||
REG_V18 = 246,
|
||||
REG_V19 = 247,
|
||||
REG_V20 = 248,
|
||||
REG_V21 = 249,
|
||||
REG_V22 = 250,
|
||||
REG_V23 = 251,
|
||||
REG_V24 = 252,
|
||||
REG_V25 = 253,
|
||||
REG_V26 = 254,
|
||||
REG_V27 = 255,
|
||||
REG_V28 = 256,
|
||||
REG_V29 = 257,
|
||||
REG_V30 = 258,
|
||||
REG_V31 = 259,
|
||||
|
||||
// pseudo registers
|
||||
REG_PC = 260,
|
||||
REG_CPACR_EL1 = 261,
|
||||
|
||||
// thread registers, depreciated, use UC_ARM64_REG_CP_REG instead
|
||||
REG_TPIDR_EL0 = 262,
|
||||
REG_TPIDRRO_EL0 = 263,
|
||||
REG_TPIDR_EL1 = 264,
|
||||
REG_PSTATE = 265,
|
||||
|
||||
// exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead
|
||||
REG_ELR_EL0 = 266,
|
||||
REG_ELR_EL1 = 267,
|
||||
REG_ELR_EL2 = 268,
|
||||
REG_ELR_EL3 = 269,
|
||||
|
||||
// stack pointers registers, depreciated, use UC_ARM64_REG_CP_REG instead
|
||||
REG_SP_EL0 = 270,
|
||||
REG_SP_EL1 = 271,
|
||||
REG_SP_EL2 = 272,
|
||||
REG_SP_EL3 = 273,
|
||||
|
||||
// other CP15 registers, depreciated, use UC_ARM64_REG_CP_REG instead
|
||||
REG_TTBR0_EL1 = 274,
|
||||
REG_TTBR1_EL1 = 275,
|
||||
REG_ESR_EL0 = 276,
|
||||
REG_ESR_EL1 = 277,
|
||||
REG_ESR_EL2 = 278,
|
||||
REG_ESR_EL3 = 279,
|
||||
REG_FAR_EL0 = 280,
|
||||
REG_FAR_EL1 = 281,
|
||||
REG_FAR_EL2 = 282,
|
||||
REG_FAR_EL3 = 283,
|
||||
REG_PAR_EL1 = 284,
|
||||
REG_MAIR_EL1 = 285,
|
||||
REG_VBAR_EL0 = 286,
|
||||
REG_VBAR_EL1 = 287,
|
||||
REG_VBAR_EL2 = 288,
|
||||
REG_VBAR_EL3 = 289,
|
||||
REG_CP_REG = 290,
|
||||
|
||||
// floating point control and status registers
|
||||
REG_FPCR = 291,
|
||||
REG_FPSR = 292,
|
||||
REG_ENDING = 293,
|
||||
|
||||
// alias registers
|
||||
REG_IP0 = 215,
|
||||
REG_IP1 = 216,
|
||||
REG_FP = 1,
|
||||
REG_LR = 2,
|
||||
|
||||
// ARM64 instructions
|
||||
|
||||
INS_INVALID = 0,
|
||||
INS_MRS = 1,
|
||||
INS_MSR = 2,
|
||||
INS_SYS = 3,
|
||||
INS_SYSL = 4,
|
||||
INS_ENDING = 5,
|
||||
}
|
||||
}
|
||||
@ -1,44 +0,0 @@
|
||||
// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
|
||||
|
||||
// ReSharper disable InconsistentNaming
|
||||
namespace Ryujinx.Tests.Unicorn.Native.Const
|
||||
{
|
||||
public enum Common
|
||||
{
|
||||
API_MAJOR = 2,
|
||||
|
||||
API_MINOR = 0,
|
||||
|
||||
API_PATCH = 0,
|
||||
API_EXTRA = 255,
|
||||
VERSION_MAJOR = 2,
|
||||
|
||||
VERSION_MINOR = 0,
|
||||
|
||||
VERSION_PATCH = 0,
|
||||
VERSION_EXTRA = 255,
|
||||
SECOND_SCALE = 1000000,
|
||||
MILISECOND_SCALE = 1000,
|
||||
QUERY_MODE = 1,
|
||||
QUERY_PAGE_SIZE = 2,
|
||||
QUERY_ARCH = 3,
|
||||
QUERY_TIMEOUT = 4,
|
||||
|
||||
CTL_IO_NONE = 0,
|
||||
CTL_IO_WRITE = 1,
|
||||
CTL_IO_READ = 2,
|
||||
CTL_IO_READ_WRITE = 3,
|
||||
|
||||
CTL_UC_MODE = 0,
|
||||
CTL_UC_PAGE_SIZE = 1,
|
||||
CTL_UC_ARCH = 2,
|
||||
CTL_UC_TIMEOUT = 3,
|
||||
CTL_UC_USE_EXITS = 4,
|
||||
CTL_UC_EXITS_CNT = 5,
|
||||
CTL_UC_EXITS = 6,
|
||||
CTL_CPU_MODEL = 7,
|
||||
CTL_TB_REQUEST_CACHE = 8,
|
||||
CTL_TB_REMOVE_CACHE = 9,
|
||||
CTL_TB_FLUSH = 10,
|
||||
}
|
||||
}
|
||||
@ -1,31 +0,0 @@
|
||||
// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
|
||||
|
||||
// ReSharper disable InconsistentNaming
|
||||
namespace Ryujinx.Tests.Unicorn.Native.Const
|
||||
{
|
||||
public enum Error
|
||||
{
|
||||
OK = 0,
|
||||
NOMEM = 1,
|
||||
ARCH = 2,
|
||||
HANDLE = 3,
|
||||
MODE = 4,
|
||||
VERSION = 5,
|
||||
READ_UNMAPPED = 6,
|
||||
WRITE_UNMAPPED = 7,
|
||||
FETCH_UNMAPPED = 8,
|
||||
HOOK = 9,
|
||||
INSN_INVALID = 10,
|
||||
MAP = 11,
|
||||
WRITE_PROT = 12,
|
||||
READ_PROT = 13,
|
||||
FETCH_PROT = 14,
|
||||
ARG = 15,
|
||||
READ_UNALIGNED = 16,
|
||||
WRITE_UNALIGNED = 17,
|
||||
FETCH_UNALIGNED = 18,
|
||||
HOOK_EXIST = 19,
|
||||
RESOURCE = 20,
|
||||
EXCEPTION = 21,
|
||||
}
|
||||
}
|
||||
@ -1,33 +0,0 @@
|
||||
// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
|
||||
|
||||
// ReSharper disable InconsistentNaming
|
||||
namespace Ryujinx.Tests.Unicorn.Native.Const
|
||||
{
|
||||
public enum Hook
|
||||
{
|
||||
INTR = 1,
|
||||
INSN = 2,
|
||||
CODE = 4,
|
||||
BLOCK = 8,
|
||||
MEM_READ_UNMAPPED = 16,
|
||||
MEM_WRITE_UNMAPPED = 32,
|
||||
MEM_FETCH_UNMAPPED = 64,
|
||||
MEM_READ_PROT = 128,
|
||||
MEM_WRITE_PROT = 256,
|
||||
MEM_FETCH_PROT = 512,
|
||||
MEM_READ = 1024,
|
||||
MEM_WRITE = 2048,
|
||||
MEM_FETCH = 4096,
|
||||
MEM_READ_AFTER = 8192,
|
||||
INSN_INVALID = 16384,
|
||||
EDGE_GENERATED = 32768,
|
||||
TCG_OPCODE = 65536,
|
||||
MEM_UNMAPPED = 112,
|
||||
MEM_PROT = 896,
|
||||
MEM_READ_INVALID = 144,
|
||||
MEM_WRITE_INVALID = 288,
|
||||
MEM_FETCH_INVALID = 576,
|
||||
MEM_INVALID = 1008,
|
||||
MEM_VALID = 7168,
|
||||
}
|
||||
}
|
||||
@ -1,19 +0,0 @@
|
||||
// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
|
||||
|
||||
// ReSharper disable InconsistentNaming
|
||||
namespace Ryujinx.Tests.Unicorn.Native.Const
|
||||
{
|
||||
public enum Memory
|
||||
{
|
||||
READ = 16,
|
||||
WRITE = 17,
|
||||
FETCH = 18,
|
||||
READ_UNMAPPED = 19,
|
||||
WRITE_UNMAPPED = 20,
|
||||
FETCH_UNMAPPED = 21,
|
||||
WRITE_PROT = 22,
|
||||
READ_PROT = 23,
|
||||
FETCH_PROT = 24,
|
||||
READ_AFTER = 25,
|
||||
}
|
||||
}
|
||||
@ -1,35 +0,0 @@
|
||||
// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
|
||||
|
||||
// ReSharper disable InconsistentNaming
|
||||
namespace Ryujinx.Tests.Unicorn.Native.Const
|
||||
{
|
||||
public enum Mode
|
||||
{
|
||||
LITTLE_ENDIAN = 0,
|
||||
BIG_ENDIAN = 1073741824,
|
||||
ARM = 0,
|
||||
THUMB = 16,
|
||||
MCLASS = 32,
|
||||
V8 = 64,
|
||||
ARMBE8 = 1024,
|
||||
ARM926 = 128,
|
||||
ARM946 = 256,
|
||||
ARM1176 = 512,
|
||||
MICRO = 16,
|
||||
MIPS3 = 32,
|
||||
MIPS32R6 = 64,
|
||||
MIPS32 = 4,
|
||||
MIPS64 = 8,
|
||||
MODE_16 = 2,
|
||||
MODE_32 = 4,
|
||||
MODE_64 = 8,
|
||||
PPC32 = 4,
|
||||
PPC64 = 8,
|
||||
QPX = 16,
|
||||
SPARC32 = 4,
|
||||
SPARC64 = 8,
|
||||
V9 = 16,
|
||||
RISCV32 = 4,
|
||||
RISCV64 = 8,
|
||||
}
|
||||
}
|
||||
@ -1,14 +0,0 @@
|
||||
// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
|
||||
|
||||
// ReSharper disable InconsistentNaming
|
||||
namespace Ryujinx.Tests.Unicorn.Native.Const
|
||||
{
|
||||
public enum Permission
|
||||
{
|
||||
NONE = 0,
|
||||
READ = 1,
|
||||
WRITE = 2,
|
||||
EXEC = 4,
|
||||
ALL = 7,
|
||||
}
|
||||
}
|
||||
@ -1,12 +0,0 @@
|
||||
// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
|
||||
|
||||
// ReSharper disable InconsistentNaming
|
||||
namespace Ryujinx.Tests.Unicorn.Native.Const
|
||||
{
|
||||
public enum TCG
|
||||
{
|
||||
OP_SUB = 0,
|
||||
OP_FLAG_CMP = 1,
|
||||
OP_FLAG_DIRECT = 2,
|
||||
}
|
||||
}
|
||||
@ -1,101 +0,0 @@
|
||||
using Ryujinx.Tests.Unicorn.Native.Const;
|
||||
using System;
|
||||
using System.Diagnostics.CodeAnalysis;
|
||||
using System.IO;
|
||||
using System.Reflection;
|
||||
using System.Runtime.CompilerServices;
|
||||
using System.Runtime.InteropServices;
|
||||
|
||||
namespace Ryujinx.Tests.Unicorn.Native
|
||||
{
|
||||
public static partial class Interface
|
||||
{
|
||||
public static bool IsUnicornAvailable { get; private set; } = true;
|
||||
|
||||
private static IntPtr ImportResolver(string libraryName, Assembly assembly, DllImportSearchPath? searchPath)
|
||||
{
|
||||
if (libraryName == "unicorn")
|
||||
{
|
||||
string loadPath = $"{Path.GetDirectoryName(assembly.Location)}/";
|
||||
loadPath += OperatingSystem.IsWindows() ? $"{libraryName}.dll" : $"lib{libraryName}.so";
|
||||
|
||||
if (!NativeLibrary.TryLoad(loadPath, out IntPtr libraryPtr))
|
||||
{
|
||||
IsUnicornAvailable = false;
|
||||
Console.Error.WriteLine($"ERROR: Could not find unicorn at: {loadPath}");
|
||||
}
|
||||
|
||||
return libraryPtr;
|
||||
}
|
||||
|
||||
// Otherwise, fallback to default import resolver.
|
||||
return IntPtr.Zero;
|
||||
}
|
||||
|
||||
static Interface()
|
||||
{
|
||||
NativeLibrary.SetDllImportResolver(Assembly.GetExecutingAssembly(), ImportResolver);
|
||||
}
|
||||
|
||||
public static void Checked(Error error)
|
||||
{
|
||||
if (error != Error.OK)
|
||||
{
|
||||
throw new UnicornException(error);
|
||||
}
|
||||
}
|
||||
|
||||
public static void MarshalArrayOf<[DynamicallyAccessedMembers(DynamicallyAccessedMemberTypes.PublicConstructors | DynamicallyAccessedMemberTypes.NonPublicConstructors)] T>(IntPtr input, int length, out T[] output)
|
||||
{
|
||||
int size = Marshal.SizeOf<T>();
|
||||
|
||||
output = new T[length];
|
||||
|
||||
for (int i = 0; i < length; i++)
|
||||
{
|
||||
IntPtr item = new IntPtr(input.ToInt64() + i * size);
|
||||
|
||||
output[i] = Marshal.PtrToStructure<T>(item);
|
||||
}
|
||||
}
|
||||
|
||||
[LibraryImport("unicorn")]
|
||||
public static partial uint uc_version(out uint major, out uint minor);
|
||||
|
||||
[LibraryImport("unicorn")]
|
||||
public static partial Error uc_open(Arch arch, Mode mode, out IntPtr uc);
|
||||
|
||||
[LibraryImport("unicorn")]
|
||||
public static partial Error uc_close(IntPtr uc);
|
||||
|
||||
[LibraryImport("unicorn")]
|
||||
public static partial IntPtr uc_strerror(Error err);
|
||||
|
||||
[LibraryImport("unicorn")]
|
||||
public static partial Error uc_reg_write(IntPtr uc, int regid, byte[] value);
|
||||
|
||||
[LibraryImport("unicorn")]
|
||||
public static partial Error uc_reg_read(IntPtr uc, int regid, byte[] value);
|
||||
|
||||
[LibraryImport("unicorn")]
|
||||
public static partial Error uc_mem_write(IntPtr uc, ulong address, byte[] bytes, ulong size);
|
||||
|
||||
[LibraryImport("unicorn")]
|
||||
public static partial Error uc_mem_read(IntPtr uc, ulong address, byte[] bytes, ulong size);
|
||||
|
||||
[LibraryImport("unicorn")]
|
||||
public static partial Error uc_emu_start(IntPtr uc, ulong begin, ulong until, ulong timeout, ulong count);
|
||||
|
||||
[LibraryImport("unicorn")]
|
||||
public static partial Error uc_mem_map(IntPtr uc, ulong address, ulong size, uint perms);
|
||||
|
||||
[LibraryImport("unicorn")]
|
||||
public static partial Error uc_mem_unmap(IntPtr uc, ulong address, ulong size);
|
||||
|
||||
[LibraryImport("unicorn")]
|
||||
public static partial Error uc_mem_protect(IntPtr uc, ulong address, ulong size, uint perms);
|
||||
|
||||
[LibraryImport("unicorn")]
|
||||
public static partial Error uc_mem_regions(IntPtr uc, out IntPtr regions, out uint count);
|
||||
}
|
||||
}
|
||||
@ -1,13 +0,0 @@
|
||||
using System;
|
||||
using System.Runtime.InteropServices;
|
||||
|
||||
namespace Ryujinx.Tests.Unicorn.Native
|
||||
{
|
||||
[StructLayout(LayoutKind.Sequential)]
|
||||
public struct UnicornMemoryRegion
|
||||
{
|
||||
public UInt64 begin; // begin address of the region (inclusive)
|
||||
public UInt64 end; // end address of the region (inclusive)
|
||||
public UInt32 perms; // memory permissions of the region
|
||||
}
|
||||
}
|
||||
@ -10,4 +10,8 @@
|
||||
<GenerateAssemblyInfo>false</GenerateAssemblyInfo>
|
||||
</PropertyGroup>
|
||||
|
||||
<ItemGroup>
|
||||
<PackageReference Include="UnicornEngine.Unicorn" />
|
||||
</ItemGroup>
|
||||
|
||||
</Project>
|
||||
|
||||
@ -1,62 +1,45 @@
|
||||
using Ryujinx.Tests.Unicorn.Native;
|
||||
using Ryujinx.Tests.Unicorn.Native.Const;
|
||||
using System;
|
||||
using System;
|
||||
using UnicornEngine.Const;
|
||||
|
||||
namespace Ryujinx.Tests.Unicorn
|
||||
{
|
||||
public class UnicornAArch32 : IDisposable
|
||||
{
|
||||
internal readonly IntPtr uc;
|
||||
private bool _isDisposed = false;
|
||||
internal readonly UnicornEngine.Unicorn uc;
|
||||
private bool _isDisposed;
|
||||
|
||||
public IndexedProperty<int, uint> R
|
||||
{
|
||||
get
|
||||
{
|
||||
return new IndexedProperty<int, uint>(
|
||||
(int i) => GetX(i),
|
||||
(int i, uint value) => SetX(i, value));
|
||||
}
|
||||
}
|
||||
public IndexedProperty<int, uint> R => new(GetX, SetX);
|
||||
|
||||
public IndexedProperty<int, SimdValue> Q
|
||||
{
|
||||
get
|
||||
{
|
||||
return new IndexedProperty<int, SimdValue>(
|
||||
(int i) => GetQ(i),
|
||||
(int i, SimdValue value) => SetQ(i, value));
|
||||
}
|
||||
}
|
||||
public IndexedProperty<int, SimdValue> Q => new(GetQ, SetQ);
|
||||
|
||||
public uint LR
|
||||
{
|
||||
get => GetRegister(Arm.REG_LR);
|
||||
set => SetRegister(Arm.REG_LR, value);
|
||||
get => GetRegister(Arm.UC_ARM_REG_LR);
|
||||
set => SetRegister(Arm.UC_ARM_REG_LR, value);
|
||||
}
|
||||
|
||||
public uint SP
|
||||
{
|
||||
get => GetRegister(Arm.REG_SP);
|
||||
set => SetRegister(Arm.REG_SP, value);
|
||||
get => GetRegister(Arm.UC_ARM_REG_SP);
|
||||
set => SetRegister(Arm.UC_ARM_REG_SP, value);
|
||||
}
|
||||
|
||||
public uint PC
|
||||
{
|
||||
get => GetRegister(Arm.REG_PC) & 0xfffffffeu;
|
||||
set => SetRegister(Arm.REG_PC, (value & 0xfffffffeu) | (ThumbFlag ? 1u : 0u));
|
||||
get => GetRegister(Arm.UC_ARM_REG_PC) & 0xfffffffeu;
|
||||
set => SetRegister(Arm.UC_ARM_REG_PC, (value & 0xfffffffeu) | (ThumbFlag ? 1u : 0u));
|
||||
}
|
||||
|
||||
public uint CPSR
|
||||
{
|
||||
get => GetRegister(Arm.REG_CPSR);
|
||||
set => SetRegister(Arm.REG_CPSR, value);
|
||||
get => GetRegister(Arm.UC_ARM_REG_CPSR);
|
||||
set => SetRegister(Arm.UC_ARM_REG_CPSR, value);
|
||||
}
|
||||
|
||||
public int Fpscr
|
||||
{
|
||||
get => (int)GetRegister(Arm.REG_FPSCR) | ((int)GetRegister(Arm.REG_FPSCR_NZCV));
|
||||
set => SetRegister(Arm.REG_FPSCR, (uint)value);
|
||||
get => (int)GetRegister(Arm.UC_ARM_REG_FPSCR) | ((int)GetRegister(Arm.UC_ARM_REG_FPSCR_NZCV));
|
||||
set => SetRegister(Arm.UC_ARM_REG_FPSCR, (uint)value);
|
||||
}
|
||||
|
||||
public bool QFlag
|
||||
@ -95,16 +78,16 @@ namespace Ryujinx.Tests.Unicorn
|
||||
set
|
||||
{
|
||||
CPSR = (CPSR & ~0x00000020u) | (value ? 0x00000020u : 0u);
|
||||
SetRegister(Arm.REG_PC, (GetRegister(Arm.REG_PC) & 0xfffffffeu) | (value ? 1u : 0u));
|
||||
SetRegister(Arm.UC_ARM_REG_PC, (GetRegister(Arm.UC_ARM_REG_PC) & 0xfffffffeu) | (value ? 1u : 0u));
|
||||
}
|
||||
}
|
||||
|
||||
public UnicornAArch32()
|
||||
{
|
||||
Interface.Checked(Interface.uc_open(Arch.ARM, Mode.LITTLE_ENDIAN, out uc));
|
||||
uc = new UnicornEngine.Unicorn(Common.UC_ARCH_ARM, Common.UC_MODE_LITTLE_ENDIAN);
|
||||
|
||||
SetRegister(Arm.REG_C1_C0_2, GetRegister(Arm.REG_C1_C0_2) | 0xf00000);
|
||||
SetRegister(Arm.REG_FPEXC, 0x40000000);
|
||||
SetRegister(Arm.UC_ARM_REG_C1_C0_2, GetRegister(Arm.UC_ARM_REG_C1_C0_2) | 0xf00000);
|
||||
SetRegister(Arm.UC_ARM_REG_FPEXC, 0x40000000);
|
||||
}
|
||||
|
||||
~UnicornAArch32()
|
||||
@ -122,14 +105,15 @@ namespace Ryujinx.Tests.Unicorn
|
||||
{
|
||||
if (!_isDisposed)
|
||||
{
|
||||
Interface.Checked(Interface.uc_close(uc));
|
||||
uc.Close();
|
||||
_isDisposed = true;
|
||||
}
|
||||
}
|
||||
|
||||
public void RunForCount(ulong count)
|
||||
{
|
||||
Interface.Checked(Interface.uc_emu_start(uc, this.PC, 0xFFFFFFFFFFFFFFFFu, 0, count));
|
||||
// FIXME: untilAddr should be 0xFFFFFFFFFFFFFFFFu
|
||||
uc.EmuStart(this.PC, -1, 0, (long)count);
|
||||
}
|
||||
|
||||
public void Step()
|
||||
@ -137,44 +121,44 @@ namespace Ryujinx.Tests.Unicorn
|
||||
RunForCount(1);
|
||||
}
|
||||
|
||||
private static Arm[] XRegisters = new Arm[16]
|
||||
private static int[] XRegisters =
|
||||
{
|
||||
Arm.REG_R0,
|
||||
Arm.REG_R1,
|
||||
Arm.REG_R2,
|
||||
Arm.REG_R3,
|
||||
Arm.REG_R4,
|
||||
Arm.REG_R5,
|
||||
Arm.REG_R6,
|
||||
Arm.REG_R7,
|
||||
Arm.REG_R8,
|
||||
Arm.REG_R9,
|
||||
Arm.REG_R10,
|
||||
Arm.REG_R11,
|
||||
Arm.REG_R12,
|
||||
Arm.REG_R13,
|
||||
Arm.REG_R14,
|
||||
Arm.REG_R15,
|
||||
Arm.UC_ARM_REG_R0,
|
||||
Arm.UC_ARM_REG_R1,
|
||||
Arm.UC_ARM_REG_R2,
|
||||
Arm.UC_ARM_REG_R3,
|
||||
Arm.UC_ARM_REG_R4,
|
||||
Arm.UC_ARM_REG_R5,
|
||||
Arm.UC_ARM_REG_R6,
|
||||
Arm.UC_ARM_REG_R7,
|
||||
Arm.UC_ARM_REG_R8,
|
||||
Arm.UC_ARM_REG_R9,
|
||||
Arm.UC_ARM_REG_R10,
|
||||
Arm.UC_ARM_REG_R11,
|
||||
Arm.UC_ARM_REG_R12,
|
||||
Arm.UC_ARM_REG_R13,
|
||||
Arm.UC_ARM_REG_R14,
|
||||
Arm.UC_ARM_REG_R15,
|
||||
};
|
||||
|
||||
private static Arm[] QRegisters = new Arm[16]
|
||||
private static int[] QRegisters =
|
||||
{
|
||||
Arm.REG_Q0,
|
||||
Arm.REG_Q1,
|
||||
Arm.REG_Q2,
|
||||
Arm.REG_Q3,
|
||||
Arm.REG_Q4,
|
||||
Arm.REG_Q5,
|
||||
Arm.REG_Q6,
|
||||
Arm.REG_Q7,
|
||||
Arm.REG_Q8,
|
||||
Arm.REG_Q9,
|
||||
Arm.REG_Q10,
|
||||
Arm.REG_Q11,
|
||||
Arm.REG_Q12,
|
||||
Arm.REG_Q13,
|
||||
Arm.REG_Q14,
|
||||
Arm.REG_Q15
|
||||
Arm.UC_ARM_REG_Q0,
|
||||
Arm.UC_ARM_REG_Q1,
|
||||
Arm.UC_ARM_REG_Q2,
|
||||
Arm.UC_ARM_REG_Q3,
|
||||
Arm.UC_ARM_REG_Q4,
|
||||
Arm.UC_ARM_REG_Q5,
|
||||
Arm.UC_ARM_REG_Q6,
|
||||
Arm.UC_ARM_REG_Q7,
|
||||
Arm.UC_ARM_REG_Q8,
|
||||
Arm.UC_ARM_REG_Q9,
|
||||
Arm.UC_ARM_REG_Q10,
|
||||
Arm.UC_ARM_REG_Q11,
|
||||
Arm.UC_ARM_REG_Q12,
|
||||
Arm.UC_ARM_REG_Q13,
|
||||
Arm.UC_ARM_REG_Q14,
|
||||
Arm.UC_ARM_REG_Q15
|
||||
};
|
||||
|
||||
public uint GetX(int index)
|
||||
@ -205,7 +189,7 @@ namespace Ryujinx.Tests.Unicorn
|
||||
}
|
||||
|
||||
// Getting quadword registers from Unicorn A32 seems to be broken, so we combine its 2 doubleword registers instead.
|
||||
return GetVector((Arm)((int)Arm.REG_D0 + index * 2));
|
||||
return GetVector(Arm.UC_ARM_REG_D0 + index * 2);
|
||||
}
|
||||
|
||||
public void SetQ(int index, SimdValue value)
|
||||
@ -215,96 +199,85 @@ namespace Ryujinx.Tests.Unicorn
|
||||
throw new ArgumentOutOfRangeException(nameof(index));
|
||||
}
|
||||
|
||||
SetVector((Arm)((int)Arm.REG_D0 + index * 2), value);
|
||||
SetVector(Arm.UC_ARM_REG_D0 + index * 2, value);
|
||||
}
|
||||
|
||||
public uint GetRegister(Arm register)
|
||||
public uint GetRegister(int register)
|
||||
{
|
||||
byte[] data = new byte[4];
|
||||
|
||||
Interface.Checked(Interface.uc_reg_read(uc, (int)register, data));
|
||||
uc.RegRead(register, data);
|
||||
|
||||
return (uint)BitConverter.ToInt32(data, 0);
|
||||
return BitConverter.ToUInt32(data, 0);
|
||||
}
|
||||
|
||||
public void SetRegister(Arm register, uint value)
|
||||
public void SetRegister(int register, uint value)
|
||||
{
|
||||
byte[] data = BitConverter.GetBytes(value);
|
||||
|
||||
Interface.Checked(Interface.uc_reg_write(uc, (int)register, data));
|
||||
uc.RegWrite(register, data);
|
||||
}
|
||||
|
||||
public SimdValue GetVector(Arm register)
|
||||
public SimdValue GetVector(int register)
|
||||
{
|
||||
byte[] data = new byte[8];
|
||||
|
||||
Interface.Checked(Interface.uc_reg_read(uc, (int)register, data));
|
||||
uc.RegRead(register, data);
|
||||
ulong lo = BitConverter.ToUInt64(data, 0);
|
||||
Interface.Checked(Interface.uc_reg_read(uc, (int)register + 1, data));
|
||||
uc.RegRead(register + 1, data);
|
||||
ulong hi = BitConverter.ToUInt64(data, 0);
|
||||
|
||||
return new SimdValue(lo, hi);
|
||||
}
|
||||
|
||||
private void SetVector(Arm register, SimdValue value)
|
||||
private void SetVector(int register, SimdValue value)
|
||||
{
|
||||
byte[] data = BitConverter.GetBytes(value.GetUInt64(0));
|
||||
Interface.Checked(Interface.uc_reg_write(uc, (int)register, data));
|
||||
uc.RegWrite(register, data);
|
||||
data = BitConverter.GetBytes(value.GetUInt64(1));
|
||||
Interface.Checked(Interface.uc_reg_write(uc, (int)register + 1, data));
|
||||
uc.RegWrite(register + 1, data);
|
||||
}
|
||||
|
||||
public byte[] MemoryRead(ulong address, ulong size)
|
||||
{
|
||||
byte[] value = new byte[size];
|
||||
|
||||
Interface.Checked(Interface.uc_mem_read(uc, address, value, size));
|
||||
uc.MemRead((long)address, value);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
public byte MemoryRead8(ulong address) => MemoryRead(address, 1)[0];
|
||||
public UInt16 MemoryRead16(ulong address) => (UInt16)BitConverter.ToInt16(MemoryRead(address, 2), 0);
|
||||
public UInt32 MemoryRead32(ulong address) => (UInt32)BitConverter.ToInt32(MemoryRead(address, 4), 0);
|
||||
public UInt64 MemoryRead64(ulong address) => (UInt64)BitConverter.ToInt64(MemoryRead(address, 8), 0);
|
||||
public ushort MemoryRead16(ulong address) => BitConverter.ToUInt16(MemoryRead(address, 2), 0);
|
||||
public uint MemoryRead32(ulong address) => BitConverter.ToUInt32(MemoryRead(address, 4), 0);
|
||||
public ulong MemoryRead64(ulong address) => BitConverter.ToUInt64(MemoryRead(address, 8), 0);
|
||||
|
||||
public void MemoryWrite(ulong address, byte[] value)
|
||||
{
|
||||
Interface.Checked(Interface.uc_mem_write(uc, address, value, (ulong)value.Length));
|
||||
uc.MemWrite((long)address, value);
|
||||
}
|
||||
|
||||
public void MemoryWrite8(ulong address, byte value) => MemoryWrite(address, new byte[] { value });
|
||||
public void MemoryWrite16(ulong address, Int16 value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
public void MemoryWrite16(ulong address, UInt16 value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
public void MemoryWrite32(ulong address, Int32 value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
public void MemoryWrite32(ulong address, UInt32 value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
public void MemoryWrite64(ulong address, Int64 value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
public void MemoryWrite64(ulong address, UInt64 value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
public void MemoryWrite8(ulong address, byte value) => MemoryWrite(address, new[] { value });
|
||||
public void MemoryWrite16(ulong address, short value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
public void MemoryWrite16(ulong address, ushort value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
public void MemoryWrite32(ulong address, int value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
public void MemoryWrite32(ulong address, uint value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
public void MemoryWrite64(ulong address, long value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
public void MemoryWrite64(ulong address, ulong value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
|
||||
public void MemoryMap(ulong address, ulong size, MemoryPermission permissions)
|
||||
{
|
||||
Interface.Checked(Interface.uc_mem_map(uc, address, size, (uint)permissions));
|
||||
uc.MemMap((long)address, (long)size, (int)permissions);
|
||||
}
|
||||
|
||||
public void MemoryUnmap(ulong address, ulong size)
|
||||
{
|
||||
Interface.Checked(Interface.uc_mem_unmap(uc, address, size));
|
||||
uc.MemUnmap((long)address, (long)size);
|
||||
}
|
||||
|
||||
public void MemoryProtect(ulong address, ulong size, MemoryPermission permissions)
|
||||
{
|
||||
Interface.Checked(Interface.uc_mem_protect(uc, address, size, (uint)permissions));
|
||||
}
|
||||
|
||||
public static bool IsAvailable()
|
||||
{
|
||||
try
|
||||
{
|
||||
Interface.uc_version(out _, out _);
|
||||
}
|
||||
catch (DllNotFoundException) { }
|
||||
|
||||
return Interface.IsUnicornAvailable;
|
||||
uc.MemProtect((long)address, (long)size, (int)permissions);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,68 +1,51 @@
|
||||
using Ryujinx.Tests.Unicorn.Native;
|
||||
using Ryujinx.Tests.Unicorn.Native.Const;
|
||||
using System;
|
||||
using UnicornEngine.Const;
|
||||
|
||||
namespace Ryujinx.Tests.Unicorn
|
||||
{
|
||||
public class UnicornAArch64 : IDisposable
|
||||
{
|
||||
internal readonly IntPtr uc;
|
||||
private bool _isDisposed = false;
|
||||
internal readonly UnicornEngine.Unicorn uc;
|
||||
private bool _isDisposed;
|
||||
|
||||
public IndexedProperty<int, ulong> X
|
||||
{
|
||||
get
|
||||
{
|
||||
return new IndexedProperty<int, ulong>(
|
||||
(int i) => GetX(i),
|
||||
(int i, ulong value) => SetX(i, value));
|
||||
}
|
||||
}
|
||||
public IndexedProperty<int, ulong> X => new(GetX, SetX);
|
||||
|
||||
public IndexedProperty<int, SimdValue> Q
|
||||
{
|
||||
get
|
||||
{
|
||||
return new IndexedProperty<int, SimdValue>(
|
||||
(int i) => GetQ(i),
|
||||
(int i, SimdValue value) => SetQ(i, value));
|
||||
}
|
||||
}
|
||||
public IndexedProperty<int, SimdValue> Q => new(GetQ, SetQ);
|
||||
|
||||
public ulong LR
|
||||
{
|
||||
get => GetRegister(Arm64.REG_LR);
|
||||
set => SetRegister(Arm64.REG_LR, value);
|
||||
get => GetRegister(Arm64.UC_ARM64_REG_LR);
|
||||
set => SetRegister(Arm64.UC_ARM64_REG_LR, value);
|
||||
}
|
||||
|
||||
public ulong SP
|
||||
{
|
||||
get => GetRegister(Arm64.REG_SP);
|
||||
set => SetRegister(Arm64.REG_SP, value);
|
||||
get => GetRegister(Arm64.UC_ARM64_REG_SP);
|
||||
set => SetRegister(Arm64.UC_ARM64_REG_SP, value);
|
||||
}
|
||||
|
||||
public ulong PC
|
||||
{
|
||||
get => GetRegister(Arm64.REG_PC);
|
||||
set => SetRegister(Arm64.REG_PC, value);
|
||||
get => GetRegister(Arm64.UC_ARM64_REG_PC);
|
||||
set => SetRegister(Arm64.UC_ARM64_REG_PC, value);
|
||||
}
|
||||
|
||||
public uint Pstate
|
||||
{
|
||||
get => (uint)GetRegister(Arm64.REG_PSTATE);
|
||||
set => SetRegister(Arm64.REG_PSTATE, (uint)value);
|
||||
get => (uint)GetRegister(Arm64.UC_ARM64_REG_PSTATE);
|
||||
set => SetRegister(Arm64.UC_ARM64_REG_PSTATE, value);
|
||||
}
|
||||
|
||||
public int Fpcr
|
||||
{
|
||||
get => (int)GetRegister(Arm64.REG_FPCR);
|
||||
set => SetRegister(Arm64.REG_FPCR, (uint)value);
|
||||
get => (int)GetRegister(Arm64.UC_ARM64_REG_FPCR);
|
||||
set => SetRegister(Arm64.UC_ARM64_REG_FPCR, (uint)value);
|
||||
}
|
||||
|
||||
public int Fpsr
|
||||
{
|
||||
get => (int)GetRegister(Arm64.REG_FPSR);
|
||||
set => SetRegister(Arm64.REG_FPSR, (uint)value);
|
||||
get => (int)GetRegister(Arm64.UC_ARM64_REG_FPSR);
|
||||
set => SetRegister(Arm64.UC_ARM64_REG_FPSR, (uint)value);
|
||||
}
|
||||
|
||||
public bool OverflowFlag
|
||||
@ -91,9 +74,9 @@ namespace Ryujinx.Tests.Unicorn
|
||||
|
||||
public UnicornAArch64()
|
||||
{
|
||||
Interface.Checked(Interface.uc_open(Arch.ARM64, Mode.LITTLE_ENDIAN, out uc));
|
||||
uc = new UnicornEngine.Unicorn(Common.UC_ARCH_ARM64, Common.UC_MODE_LITTLE_ENDIAN);
|
||||
|
||||
SetRegister(Arm64.REG_CPACR_EL1, 0x00300000);
|
||||
SetRegister(Arm64.UC_ARM64_REG_CPACR_EL1, 0x00300000);
|
||||
}
|
||||
|
||||
~UnicornAArch64()
|
||||
@ -111,14 +94,15 @@ namespace Ryujinx.Tests.Unicorn
|
||||
{
|
||||
if (!_isDisposed)
|
||||
{
|
||||
Interface.Checked(Interface.uc_close(uc));
|
||||
uc.Close();
|
||||
_isDisposed = true;
|
||||
}
|
||||
}
|
||||
|
||||
public void RunForCount(ulong count)
|
||||
{
|
||||
Interface.Checked(Interface.uc_emu_start(uc, this.PC, 0xFFFFFFFFFFFFFFFFu, 0, count));
|
||||
// FIXME: untilAddr should be 0xFFFFFFFFFFFFFFFFul
|
||||
uc.EmuStart((long)this.PC, -1, 0, (long)count);
|
||||
}
|
||||
|
||||
public void Step()
|
||||
@ -126,75 +110,75 @@ namespace Ryujinx.Tests.Unicorn
|
||||
RunForCount(1);
|
||||
}
|
||||
|
||||
private static Arm64[] XRegisters = new Arm64[31]
|
||||
private static int[] XRegisters =
|
||||
{
|
||||
Arm64.REG_X0,
|
||||
Arm64.REG_X1,
|
||||
Arm64.REG_X2,
|
||||
Arm64.REG_X3,
|
||||
Arm64.REG_X4,
|
||||
Arm64.REG_X5,
|
||||
Arm64.REG_X6,
|
||||
Arm64.REG_X7,
|
||||
Arm64.REG_X8,
|
||||
Arm64.REG_X9,
|
||||
Arm64.REG_X10,
|
||||
Arm64.REG_X11,
|
||||
Arm64.REG_X12,
|
||||
Arm64.REG_X13,
|
||||
Arm64.REG_X14,
|
||||
Arm64.REG_X15,
|
||||
Arm64.REG_X16,
|
||||
Arm64.REG_X17,
|
||||
Arm64.REG_X18,
|
||||
Arm64.REG_X19,
|
||||
Arm64.REG_X20,
|
||||
Arm64.REG_X21,
|
||||
Arm64.REG_X22,
|
||||
Arm64.REG_X23,
|
||||
Arm64.REG_X24,
|
||||
Arm64.REG_X25,
|
||||
Arm64.REG_X26,
|
||||
Arm64.REG_X27,
|
||||
Arm64.REG_X28,
|
||||
Arm64.REG_X29,
|
||||
Arm64.REG_X30,
|
||||
Arm64.UC_ARM64_REG_X0,
|
||||
Arm64.UC_ARM64_REG_X1,
|
||||
Arm64.UC_ARM64_REG_X2,
|
||||
Arm64.UC_ARM64_REG_X3,
|
||||
Arm64.UC_ARM64_REG_X4,
|
||||
Arm64.UC_ARM64_REG_X5,
|
||||
Arm64.UC_ARM64_REG_X6,
|
||||
Arm64.UC_ARM64_REG_X7,
|
||||
Arm64.UC_ARM64_REG_X8,
|
||||
Arm64.UC_ARM64_REG_X9,
|
||||
Arm64.UC_ARM64_REG_X10,
|
||||
Arm64.UC_ARM64_REG_X11,
|
||||
Arm64.UC_ARM64_REG_X12,
|
||||
Arm64.UC_ARM64_REG_X13,
|
||||
Arm64.UC_ARM64_REG_X14,
|
||||
Arm64.UC_ARM64_REG_X15,
|
||||
Arm64.UC_ARM64_REG_X16,
|
||||
Arm64.UC_ARM64_REG_X17,
|
||||
Arm64.UC_ARM64_REG_X18,
|
||||
Arm64.UC_ARM64_REG_X19,
|
||||
Arm64.UC_ARM64_REG_X20,
|
||||
Arm64.UC_ARM64_REG_X21,
|
||||
Arm64.UC_ARM64_REG_X22,
|
||||
Arm64.UC_ARM64_REG_X23,
|
||||
Arm64.UC_ARM64_REG_X24,
|
||||
Arm64.UC_ARM64_REG_X25,
|
||||
Arm64.UC_ARM64_REG_X26,
|
||||
Arm64.UC_ARM64_REG_X27,
|
||||
Arm64.UC_ARM64_REG_X28,
|
||||
Arm64.UC_ARM64_REG_X29,
|
||||
Arm64.UC_ARM64_REG_X30,
|
||||
};
|
||||
|
||||
private static Arm64[] QRegisters = new Arm64[32]
|
||||
private static int[] QRegisters =
|
||||
{
|
||||
Arm64.REG_Q0,
|
||||
Arm64.REG_Q1,
|
||||
Arm64.REG_Q2,
|
||||
Arm64.REG_Q3,
|
||||
Arm64.REG_Q4,
|
||||
Arm64.REG_Q5,
|
||||
Arm64.REG_Q6,
|
||||
Arm64.REG_Q7,
|
||||
Arm64.REG_Q8,
|
||||
Arm64.REG_Q9,
|
||||
Arm64.REG_Q10,
|
||||
Arm64.REG_Q11,
|
||||
Arm64.REG_Q12,
|
||||
Arm64.REG_Q13,
|
||||
Arm64.REG_Q14,
|
||||
Arm64.REG_Q15,
|
||||
Arm64.REG_Q16,
|
||||
Arm64.REG_Q17,
|
||||
Arm64.REG_Q18,
|
||||
Arm64.REG_Q19,
|
||||
Arm64.REG_Q20,
|
||||
Arm64.REG_Q21,
|
||||
Arm64.REG_Q22,
|
||||
Arm64.REG_Q23,
|
||||
Arm64.REG_Q24,
|
||||
Arm64.REG_Q25,
|
||||
Arm64.REG_Q26,
|
||||
Arm64.REG_Q27,
|
||||
Arm64.REG_Q28,
|
||||
Arm64.REG_Q29,
|
||||
Arm64.REG_Q30,
|
||||
Arm64.REG_Q31,
|
||||
Arm64.UC_ARM64_REG_Q0,
|
||||
Arm64.UC_ARM64_REG_Q1,
|
||||
Arm64.UC_ARM64_REG_Q2,
|
||||
Arm64.UC_ARM64_REG_Q3,
|
||||
Arm64.UC_ARM64_REG_Q4,
|
||||
Arm64.UC_ARM64_REG_Q5,
|
||||
Arm64.UC_ARM64_REG_Q6,
|
||||
Arm64.UC_ARM64_REG_Q7,
|
||||
Arm64.UC_ARM64_REG_Q8,
|
||||
Arm64.UC_ARM64_REG_Q9,
|
||||
Arm64.UC_ARM64_REG_Q10,
|
||||
Arm64.UC_ARM64_REG_Q11,
|
||||
Arm64.UC_ARM64_REG_Q12,
|
||||
Arm64.UC_ARM64_REG_Q13,
|
||||
Arm64.UC_ARM64_REG_Q14,
|
||||
Arm64.UC_ARM64_REG_Q15,
|
||||
Arm64.UC_ARM64_REG_Q16,
|
||||
Arm64.UC_ARM64_REG_Q17,
|
||||
Arm64.UC_ARM64_REG_Q18,
|
||||
Arm64.UC_ARM64_REG_Q19,
|
||||
Arm64.UC_ARM64_REG_Q20,
|
||||
Arm64.UC_ARM64_REG_Q21,
|
||||
Arm64.UC_ARM64_REG_Q22,
|
||||
Arm64.UC_ARM64_REG_Q23,
|
||||
Arm64.UC_ARM64_REG_Q24,
|
||||
Arm64.UC_ARM64_REG_Q25,
|
||||
Arm64.UC_ARM64_REG_Q26,
|
||||
Arm64.UC_ARM64_REG_Q27,
|
||||
Arm64.UC_ARM64_REG_Q28,
|
||||
Arm64.UC_ARM64_REG_Q29,
|
||||
Arm64.UC_ARM64_REG_Q30,
|
||||
Arm64.UC_ARM64_REG_Q31,
|
||||
};
|
||||
|
||||
public ulong GetX(int index)
|
||||
@ -237,89 +221,78 @@ namespace Ryujinx.Tests.Unicorn
|
||||
SetVector(QRegisters[index], value);
|
||||
}
|
||||
|
||||
private ulong GetRegister(Arm64 register)
|
||||
private ulong GetRegister(int register)
|
||||
{
|
||||
byte[] data = new byte[8];
|
||||
|
||||
Interface.Checked(Interface.uc_reg_read(uc, (int)register, data));
|
||||
uc.RegRead(register, data);
|
||||
|
||||
return (ulong)BitConverter.ToInt64(data, 0);
|
||||
return BitConverter.ToUInt64(data, 0);
|
||||
}
|
||||
|
||||
private void SetRegister(Arm64 register, ulong value)
|
||||
private void SetRegister(int register, ulong value)
|
||||
{
|
||||
byte[] data = BitConverter.GetBytes(value);
|
||||
|
||||
Interface.Checked(Interface.uc_reg_write(uc, (int)register, data));
|
||||
uc.RegWrite(register, data);
|
||||
}
|
||||
|
||||
private SimdValue GetVector(Arm64 register)
|
||||
private SimdValue GetVector(int register)
|
||||
{
|
||||
byte[] data = new byte[16];
|
||||
|
||||
Interface.Checked(Interface.uc_reg_read(uc, (int)register, data));
|
||||
uc.RegRead(register, data);
|
||||
|
||||
return new SimdValue(data);
|
||||
}
|
||||
|
||||
private void SetVector(Arm64 register, SimdValue value)
|
||||
private void SetVector(int register, SimdValue value)
|
||||
{
|
||||
byte[] data = value.ToArray();
|
||||
|
||||
Interface.Checked(Interface.uc_reg_write(uc, (int)register, data));
|
||||
uc.RegWrite(register, data);
|
||||
}
|
||||
|
||||
public byte[] MemoryRead(ulong address, ulong size)
|
||||
{
|
||||
byte[] value = new byte[size];
|
||||
|
||||
Interface.Checked(Interface.uc_mem_read(uc, address, value, size));
|
||||
uc.MemRead((long)address, value);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
public byte MemoryRead8 (ulong address) => MemoryRead(address, 1)[0];
|
||||
public UInt16 MemoryRead16(ulong address) => (UInt16)BitConverter.ToInt16(MemoryRead(address, 2), 0);
|
||||
public UInt32 MemoryRead32(ulong address) => (UInt32)BitConverter.ToInt32(MemoryRead(address, 4), 0);
|
||||
public UInt64 MemoryRead64(ulong address) => (UInt64)BitConverter.ToInt64(MemoryRead(address, 8), 0);
|
||||
public ushort MemoryRead16(ulong address) => BitConverter.ToUInt16(MemoryRead(address, 2), 0);
|
||||
public uint MemoryRead32(ulong address) => BitConverter.ToUInt32(MemoryRead(address, 4), 0);
|
||||
public ulong MemoryRead64(ulong address) => BitConverter.ToUInt64(MemoryRead(address, 8), 0);
|
||||
|
||||
public void MemoryWrite(ulong address, byte[] value)
|
||||
{
|
||||
Interface.Checked(Interface.uc_mem_write(uc, address, value, (ulong)value.Length));
|
||||
uc.MemWrite((long)address, value);
|
||||
}
|
||||
|
||||
public void MemoryWrite8 (ulong address, byte value) => MemoryWrite(address, new byte[]{value});
|
||||
public void MemoryWrite16(ulong address, Int16 value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
public void MemoryWrite16(ulong address, UInt16 value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
public void MemoryWrite32(ulong address, Int32 value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
public void MemoryWrite32(ulong address, UInt32 value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
public void MemoryWrite64(ulong address, Int64 value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
public void MemoryWrite64(ulong address, UInt64 value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
public void MemoryWrite8 (ulong address, byte value) => MemoryWrite(address, new[]{ value });
|
||||
public void MemoryWrite16(ulong address, short value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
public void MemoryWrite16(ulong address, ushort value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
public void MemoryWrite32(ulong address, int value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
public void MemoryWrite32(ulong address, uint value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
public void MemoryWrite64(ulong address, long value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
public void MemoryWrite64(ulong address, ulong value) => MemoryWrite(address, BitConverter.GetBytes(value));
|
||||
|
||||
public void MemoryMap(ulong address, ulong size, MemoryPermission permissions)
|
||||
{
|
||||
Interface.Checked(Interface.uc_mem_map(uc, address, size, (uint)permissions));
|
||||
uc.MemMap((long)address, (long)size, (int)permissions);
|
||||
}
|
||||
|
||||
public void MemoryUnmap(ulong address, ulong size)
|
||||
{
|
||||
Interface.Checked(Interface.uc_mem_unmap(uc, address, size));
|
||||
uc.MemUnmap((long)address, (long)size);
|
||||
}
|
||||
|
||||
public void MemoryProtect(ulong address, ulong size, MemoryPermission permissions)
|
||||
{
|
||||
Interface.Checked(Interface.uc_mem_protect(uc, address, size, (uint)permissions));
|
||||
}
|
||||
|
||||
public static bool IsAvailable()
|
||||
{
|
||||
try
|
||||
{
|
||||
Interface.uc_version(out _, out _);
|
||||
}
|
||||
catch (DllNotFoundException) { }
|
||||
|
||||
return Interface.IsUnicornAvailable;
|
||||
uc.MemProtect((long)address, (long)size, (int)permissions);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,24 +0,0 @@
|
||||
using Ryujinx.Tests.Unicorn.Native.Const;
|
||||
using System;
|
||||
using System.Runtime.InteropServices;
|
||||
|
||||
namespace Ryujinx.Tests.Unicorn
|
||||
{
|
||||
public class UnicornException : Exception
|
||||
{
|
||||
public readonly Error Error;
|
||||
|
||||
internal UnicornException(Error error)
|
||||
{
|
||||
Error = error;
|
||||
}
|
||||
|
||||
public override string Message
|
||||
{
|
||||
get
|
||||
{
|
||||
return Marshal.PtrToStringAnsi(Native.Interface.uc_strerror(Error));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,20 +0,0 @@
|
||||
# Unicorn
|
||||
|
||||
Unicorn is a CPU simulator with bindings in many languages, including
|
||||
C#/.NET.
|
||||
It is used by the Ryujinx test suite for comparative testing with its built-in
|
||||
CPU simulator, Armeilleure.
|
||||
|
||||
## Windows
|
||||
|
||||
On Windows, Unicorn is shipped as a pre-compiled dynamic library (`.dll`), licenced under the GPLv2.
|
||||
|
||||
The source code for `windows/unicorn.dll` is available at: https://github.com/unicorn-engine/unicorn/tree/df3aa0fccbce9e1420e82110cbae5951755a0698
|
||||
|
||||
## Linux
|
||||
|
||||
On Windows, Unicorn is shipped as a pre-compiled shared object (`.so`), licenced under the GPLv2.
|
||||
|
||||
The source code for `linux/unicorn.so` is available at: https://github.com/unicorn-engine/unicorn/tree/df3aa0fccbce9e1420e82110cbae5951755a0698
|
||||
|
||||
See https://github.com/Ryujinx/Ryujinx/pull/1433 for details.
|
||||
Binary file not shown.
Binary file not shown.
@ -1,199 +0,0 @@
|
||||
#!/usr/bin/env python3
|
||||
# Unicorn Engine
|
||||
# By Dang Hoang Vu, 2013
|
||||
# Modified for Ryujinx from: https://github.com/unicorn-engine/unicorn/blob/6c1cbef6ac505d355033aef1176b684d02e1eb3a/bindings/const_generator.py
|
||||
from __future__ import print_function
|
||||
import sys, re, os
|
||||
|
||||
include = [ 'arm.h', 'arm64.h', 'unicorn.h' ]
|
||||
split_common = [ 'ARCH', 'MODE', 'ERR', 'MEM', 'TCG', 'HOOK', 'PROT' ]
|
||||
|
||||
template = {
|
||||
'dotnet': {
|
||||
'header': "// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT\n\n// ReSharper disable InconsistentNaming\nnamespace Ryujinx.Tests.Unicorn.Native.Const\n{\n public enum %s\n {\n",
|
||||
'footer': " }\n}\n",
|
||||
'line_format': ' %s = %s,\n',
|
||||
'out_file': os.path.join(os.path.dirname(__file__), 'Native', 'Const', '%s.cs'),
|
||||
# prefixes for constant filenames of all archs - case sensitive
|
||||
'arm.h': 'Arm',
|
||||
'arm64.h': 'Arm64',
|
||||
'unicorn.h': 'Common',
|
||||
# prefixes for filenames of split_common values - case sensitive
|
||||
'ARCH': 'Arch',
|
||||
'MODE': 'Mode',
|
||||
'ERR': 'Error',
|
||||
'MEM': 'Memory',
|
||||
'TCG': 'TCG',
|
||||
'HOOK': 'Hook',
|
||||
'PROT': 'Permission',
|
||||
'comment_open': ' //',
|
||||
'comment_close': '',
|
||||
}
|
||||
}
|
||||
|
||||
# markup for comments to be added to autogen files
|
||||
MARKUP = '//>'
|
||||
|
||||
def gen(unicorn_repo_path):
|
||||
global include
|
||||
include_dir = os.path.join(unicorn_repo_path, 'include', 'unicorn')
|
||||
templ = template["dotnet"]
|
||||
for target in include:
|
||||
prefix = templ[target]
|
||||
outfile = open(templ['out_file'] %(prefix), 'wb') # open as binary prevents windows newlines
|
||||
outfile.write((templ['header'] % (prefix)).encode("utf-8"))
|
||||
if target == 'unicorn.h':
|
||||
prefix = ''
|
||||
for cat in split_common:
|
||||
with open(templ['out_file'] %(templ[cat]), 'wb') as file:
|
||||
file.write((templ['header'] %(templ[cat])).encode("utf-8"))
|
||||
with open(os.path.join(include_dir, target)) as f:
|
||||
lines = f.readlines()
|
||||
|
||||
previous = {}
|
||||
count = 0
|
||||
skip = 0
|
||||
in_comment = False
|
||||
|
||||
for lno, line in enumerate(lines):
|
||||
if "/*" in line:
|
||||
in_comment = True
|
||||
if "*/" in line:
|
||||
in_comment = False
|
||||
if in_comment:
|
||||
continue
|
||||
if skip > 0:
|
||||
# Due to clang-format, values may come up in the next line
|
||||
skip -= 1
|
||||
continue
|
||||
line = line.strip()
|
||||
|
||||
if line.startswith(MARKUP): # markup for comments
|
||||
outfile.write(("\n%s%s%s\n" %(templ['comment_open'], \
|
||||
line.replace(MARKUP, ''), templ['comment_close'])).encode("utf-8"))
|
||||
continue
|
||||
|
||||
if line == '' or line.startswith('//'):
|
||||
continue
|
||||
|
||||
tmp = line.strip().split(',')
|
||||
if len(tmp) >= 2 and tmp[0] != "#define" and not tmp[0].startswith("UC_"):
|
||||
continue
|
||||
for t in tmp:
|
||||
t = t.strip()
|
||||
if not t or t.startswith('//'): continue
|
||||
f = re.split('\s+', t)
|
||||
|
||||
# parse #define UC_TARGET (num)
|
||||
define = False
|
||||
if f[0] == '#define' and len(f) >= 3:
|
||||
define = True
|
||||
f.pop(0)
|
||||
f.insert(1, '=')
|
||||
if f[0].startswith("UC_" + prefix.upper()) or f[0].startswith("UC_CPU"):
|
||||
if len(f) > 1 and f[1] not in ('//', '='):
|
||||
print("WARNING: Unable to convert %s" % f)
|
||||
print(" Line =", line)
|
||||
continue
|
||||
elif len(f) > 1 and f[1] == '=':
|
||||
# Like:
|
||||
# UC_A =
|
||||
# (1 << 2)
|
||||
# #define UC_B \
|
||||
# (UC_A | UC_C)
|
||||
# Let's search the next line
|
||||
if len(f) == 2:
|
||||
if lno == len(lines) - 1:
|
||||
print("WARNING: Unable to convert %s" % f)
|
||||
print(" Line =", line)
|
||||
continue
|
||||
skip += 1
|
||||
next_line = lines[lno + 1]
|
||||
next_line_tmp = next_line.strip().split(",")
|
||||
rhs = next_line_tmp[0]
|
||||
elif f[-1] == "\\":
|
||||
idx = 0
|
||||
rhs = ""
|
||||
while True:
|
||||
idx += 1
|
||||
if lno + idx == len(lines):
|
||||
print("WARNING: Unable to convert %s" % f)
|
||||
print(" Line =", line)
|
||||
continue
|
||||
skip += 1
|
||||
next_line = lines[lno + idx]
|
||||
next_line_f = re.split('\s+', next_line.strip())
|
||||
if next_line_f[-1] == "\\":
|
||||
rhs += "".join(next_line_f[:-1])
|
||||
else:
|
||||
rhs += next_line.strip()
|
||||
break
|
||||
else:
|
||||
rhs = ''.join(f[2:])
|
||||
else:
|
||||
rhs = str(count)
|
||||
|
||||
|
||||
lhs = f[0].strip()
|
||||
#print(f'lhs: {lhs} rhs: {rhs} f:{f}')
|
||||
# evaluate bitshifts in constants e.g. "UC_X86 = 1 << 1"
|
||||
match = re.match(r'(?P<rhs>\s*\d+\s*<<\s*\d+\s*)', rhs)
|
||||
if match:
|
||||
rhs = str(eval(match.group(1)))
|
||||
else:
|
||||
# evaluate references to other constants e.g. "UC_ARM_REG_X = UC_ARM_REG_SP"
|
||||
match = re.match(r'^([^\d]\w+)$', rhs)
|
||||
if match:
|
||||
rhs = previous[match.group(1)]
|
||||
|
||||
if not rhs.isdigit():
|
||||
for k, v in previous.items():
|
||||
rhs = re.sub(r'\b%s\b' % k, v, rhs)
|
||||
rhs = str(eval(rhs))
|
||||
|
||||
lhs_strip = re.sub(r'^UC_', '', lhs)
|
||||
count = int(rhs) + 1
|
||||
|
||||
if target == "unicorn.h":
|
||||
matched_cat = False
|
||||
for cat in split_common:
|
||||
if lhs_strip.startswith(f"{cat}_"):
|
||||
with open(templ['out_file'] %(templ[cat]), 'ab') as cat_file:
|
||||
cat_lhs_strip = lhs_strip
|
||||
if not lhs_strip.lstrip(f"{cat}_").isnumeric():
|
||||
cat_lhs_strip = lhs_strip.replace(f"{cat}_", "", 1)
|
||||
cat_file.write(
|
||||
(templ['line_format'] % (cat_lhs_strip, rhs)).encode("utf-8"))
|
||||
matched_cat = True
|
||||
break
|
||||
if matched_cat:
|
||||
previous[lhs] = str(rhs)
|
||||
continue
|
||||
|
||||
if (count == 1):
|
||||
outfile.write(("\n").encode("utf-8"))
|
||||
|
||||
if lhs_strip.startswith(f"{prefix.upper()}_") and not lhs_strip.replace(f"{prefix.upper()}_", "", 1).isnumeric():
|
||||
lhs_strip = lhs_strip.replace(f"{prefix.upper()}_", "", 1)
|
||||
|
||||
outfile.write((templ['line_format'] % (lhs_strip, rhs)).encode("utf-8"))
|
||||
previous[lhs] = str(rhs)
|
||||
|
||||
outfile.write((templ['footer']).encode("utf-8"))
|
||||
outfile.close()
|
||||
|
||||
if target == "unicorn.h":
|
||||
for cat in split_common:
|
||||
with open(templ['out_file'] %(templ[cat]), 'ab') as cat_file:
|
||||
cat_file.write(templ['footer'].encode('utf-8'))
|
||||
|
||||
if __name__ == "__main__":
|
||||
if len(sys.argv) < 2:
|
||||
print("Usage:", sys.argv[0], " <path to unicorn repo>")
|
||||
sys.exit(1)
|
||||
unicorn_repo_path = sys.argv[1]
|
||||
if os.path.isdir(unicorn_repo_path):
|
||||
print("Generating constants for dotnet")
|
||||
gen(unicorn_repo_path)
|
||||
else:
|
||||
print("Couldn't find unicorn repo at:", unicorn_repo_path)
|
||||
Reference in New Issue
Block a user