mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2025-06-28 04:20:46 -07:00
[ARMeilleure] Address dotnet-format issues (#5357)
* dotnet format style --severity info Some changes were manually reverted. * dotnet format analyzers --serverity info Some changes have been minimally adapted. * Restore a few unused methods and variables * Silence dotnet format IDE0060 warnings * Silence dotnet format IDE0052 warnings * Address or silence dotnet format IDE1006 warnings * Address or silence dotnet format CA2208 warnings * Address dotnet format CA1822 warnings * Address or silence dotnet format CA1069 warnings * Silence CA1806 and CA1834 issues * Address dotnet format CA1401 warnings * Fix new dotnet-format issues after rebase * Address review comments * Address dotnet format CA2208 warnings properly * Fix formatting for switch expressions * Address most dotnet format whitespace warnings * Apply dotnet format whitespace formatting A few of them have been manually reverted and the corresponding warning was silenced * Add previously silenced warnings back I have no clue how these disappeared * Revert formatting changes for OpCodeTable.cs * Enable formatting for a few cases again * Format if-blocks correctly * Enable formatting for a few more cases again * Fix inline comment alignment * Run dotnet format after rebase and remove unused usings - analyzers - style - whitespace * Disable 'prefer switch expression' rule * Add comments to disabled warnings * Remove a few unused parameters * Adjust namespaces * Simplify properties and array initialization, Use const when possible, Remove trailing commas * Start working on disabled warnings * Fix and silence a few dotnet-format warnings again * Address IDE0251 warnings * Address a few disabled IDE0060 warnings * Silence IDE0060 in .editorconfig * Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas" This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e. * dotnet format whitespace after rebase * First dotnet format pass * Remove unnecessary formatting exclusion * Add unsafe dotnet format changes * Change visibility of JitSupportDarwin to internal
This commit is contained in:
TSRBerry
GitHub
@ -104,11 +104,11 @@ namespace ARMeilleure.CodeGen.X86
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case Instruction.Tailcall:
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if (callConv == CallConvName.Windows)
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{
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PreAllocatorWindows.InsertTailcallCopies(block.Operations, stackAlloc, node);
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PreAllocatorWindows.InsertTailcallCopies(block.Operations, node);
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}
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else
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{
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PreAllocatorSystemV.InsertTailcallCopies(block.Operations, stackAlloc, node);
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PreAllocatorSystemV.InsertTailcallCopies(block.Operations, node);
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}
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break;
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@ -177,10 +177,7 @@ namespace ARMeilleure.CodeGen.X86
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{
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src2 = node.GetSource(1);
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Operand temp = src1;
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src1 = src2;
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src2 = temp;
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(src2, src1) = (src1, src2);
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node.SetSource(0, src1);
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node.SetSource(1, src2);
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@ -228,151 +225,151 @@ namespace ARMeilleure.CodeGen.X86
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case Instruction.CompareAndSwap:
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case Instruction.CompareAndSwap16:
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case Instruction.CompareAndSwap8:
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{
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OperandType type = node.GetSource(1).Type;
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if (type == OperandType.V128)
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{
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// Handle the many restrictions of the compare and exchange (16 bytes) instruction:
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// - The expected value should be in RDX:RAX.
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// - The new value to be written should be in RCX:RBX.
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// - The value at the memory location is loaded to RDX:RAX.
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void SplitOperand(Operand source, Operand lr, Operand hr)
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OperandType type = node.GetSource(1).Type;
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if (type == OperandType.V128)
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{
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nodes.AddBefore(node, Operation(Instruction.VectorExtract, lr, source, Const(0)));
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nodes.AddBefore(node, Operation(Instruction.VectorExtract, hr, source, Const(1)));
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// Handle the many restrictions of the compare and exchange (16 bytes) instruction:
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// - The expected value should be in RDX:RAX.
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// - The new value to be written should be in RCX:RBX.
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// - The value at the memory location is loaded to RDX:RAX.
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void SplitOperand(Operand source, Operand lr, Operand hr)
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{
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nodes.AddBefore(node, Operation(Instruction.VectorExtract, lr, source, Const(0)));
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nodes.AddBefore(node, Operation(Instruction.VectorExtract, hr, source, Const(1)));
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}
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Operand rax = Gpr(X86Register.Rax, OperandType.I64);
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Operand rbx = Gpr(X86Register.Rbx, OperandType.I64);
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Operand rcx = Gpr(X86Register.Rcx, OperandType.I64);
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Operand rdx = Gpr(X86Register.Rdx, OperandType.I64);
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SplitOperand(node.GetSource(1), rax, rdx);
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SplitOperand(node.GetSource(2), rbx, rcx);
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Operation operation = node;
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node = nodes.AddAfter(node, Operation(Instruction.VectorCreateScalar, dest, rax));
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nodes.AddAfter(node, Operation(Instruction.VectorInsert, dest, dest, rdx, Const(1)));
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operation.SetDestinations(new Operand[] { rdx, rax });
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operation.SetSources(new Operand[] { operation.GetSource(0), rdx, rax, rcx, rbx });
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}
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else
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{
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// Handle the many restrictions of the compare and exchange (32/64) instruction:
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// - The expected value should be in (E/R)AX.
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// - The value at the memory location is loaded to (E/R)AX.
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Operand expected = node.GetSource(1);
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Operand newValue = node.GetSource(2);
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Operand rax = Gpr(X86Register.Rax, expected.Type);
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nodes.AddBefore(node, Operation(Instruction.Copy, rax, expected));
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// We need to store the new value into a temp, since it may
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// be a constant, and this instruction does not support immediate operands.
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Operand temp = Local(newValue.Type);
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nodes.AddBefore(node, Operation(Instruction.Copy, temp, newValue));
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node.SetSources(new Operand[] { node.GetSource(0), rax, temp });
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nodes.AddAfter(node, Operation(Instruction.Copy, dest, rax));
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node.Destination = rax;
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}
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Operand rax = Gpr(X86Register.Rax, OperandType.I64);
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Operand rbx = Gpr(X86Register.Rbx, OperandType.I64);
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Operand rcx = Gpr(X86Register.Rcx, OperandType.I64);
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Operand rdx = Gpr(X86Register.Rdx, OperandType.I64);
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SplitOperand(node.GetSource(1), rax, rdx);
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SplitOperand(node.GetSource(2), rbx, rcx);
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Operation operation = node;
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node = nodes.AddAfter(node, Operation(Instruction.VectorCreateScalar, dest, rax));
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nodes.AddAfter(node, Operation(Instruction.VectorInsert, dest, dest, rdx, Const(1)));
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operation.SetDestinations(new Operand[] { rdx, rax });
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operation.SetSources(new Operand[] { operation.GetSource(0), rdx, rax, rcx, rbx });
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break;
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}
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else
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{
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// Handle the many restrictions of the compare and exchange (32/64) instruction:
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// - The expected value should be in (E/R)AX.
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// - The value at the memory location is loaded to (E/R)AX.
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Operand expected = node.GetSource(1);
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Operand newValue = node.GetSource(2);
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Operand rax = Gpr(X86Register.Rax, expected.Type);
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nodes.AddBefore(node, Operation(Instruction.Copy, rax, expected));
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// We need to store the new value into a temp, since it may
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// be a constant, and this instruction does not support immediate operands.
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Operand temp = Local(newValue.Type);
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nodes.AddBefore(node, Operation(Instruction.Copy, temp, newValue));
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node.SetSources(new Operand[] { node.GetSource(0), rax, temp });
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nodes.AddAfter(node, Operation(Instruction.Copy, dest, rax));
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node.Destination = rax;
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}
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break;
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}
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case Instruction.Divide:
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case Instruction.DivideUI:
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{
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// Handle the many restrictions of the division instructions:
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// - The dividend is always in RDX:RAX.
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// - The result is always in RAX.
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// - Additionally it also writes the remainder in RDX.
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if (dest.Type.IsInteger())
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{
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// Handle the many restrictions of the division instructions:
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// - The dividend is always in RDX:RAX.
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// - The result is always in RAX.
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// - Additionally it also writes the remainder in RDX.
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if (dest.Type.IsInteger())
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{
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Operand src1 = node.GetSource(0);
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Operand rax = Gpr(X86Register.Rax, src1.Type);
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Operand rdx = Gpr(X86Register.Rdx, src1.Type);
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nodes.AddBefore(node, Operation(Instruction.Copy, rax, src1));
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nodes.AddBefore(node, Operation(Instruction.Clobber, rdx));
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nodes.AddAfter(node, Operation(Instruction.Copy, dest, rax));
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node.SetSources(new Operand[] { rdx, rax, node.GetSource(1) });
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node.Destination = rax;
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}
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break;
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}
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case Instruction.Extended:
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{
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bool isBlend = node.Intrinsic == Intrinsic.X86Blendvpd ||
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node.Intrinsic == Intrinsic.X86Blendvps ||
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node.Intrinsic == Intrinsic.X86Pblendvb;
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// BLENDVPD, BLENDVPS, PBLENDVB last operand is always implied to be XMM0 when VEX is not supported.
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// SHA256RNDS2 always has an implied XMM0 as a last operand.
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if ((isBlend && !HardwareCapabilities.SupportsVexEncoding) || node.Intrinsic == Intrinsic.X86Sha256Rnds2)
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{
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Operand xmm0 = Xmm(X86Register.Xmm0, OperandType.V128);
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nodes.AddBefore(node, Operation(Instruction.Copy, xmm0, node.GetSource(2)));
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node.SetSource(2, xmm0);
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}
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break;
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}
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case Instruction.Multiply64HighSI:
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case Instruction.Multiply64HighUI:
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{
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// Handle the many restrictions of the i64 * i64 = i128 multiply instructions:
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// - The multiplicand is always in RAX.
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// - The lower 64-bits of the result is always in RAX.
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// - The higher 64-bits of the result is always in RDX.
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Operand src1 = node.GetSource(0);
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Operand rax = Gpr(X86Register.Rax, src1.Type);
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Operand rdx = Gpr(X86Register.Rdx, src1.Type);
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nodes.AddBefore(node, Operation(Instruction.Copy, rax, src1));
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nodes.AddBefore(node, Operation(Instruction.Clobber, rdx));
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nodes.AddBefore(node, Operation(Instruction.Copy, rax, src1));
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nodes.AddAfter(node, Operation(Instruction.Copy, dest, rax));
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node.SetSource(0, rax);
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node.SetSources(new Operand[] { rdx, rax, node.GetSource(1) });
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node.Destination = rax;
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nodes.AddAfter(node, Operation(Instruction.Copy, dest, rdx));
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node.SetDestinations(new Operand[] { rdx, rax });
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break;
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}
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break;
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}
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case Instruction.Extended:
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{
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bool isBlend = node.Intrinsic == Intrinsic.X86Blendvpd ||
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node.Intrinsic == Intrinsic.X86Blendvps ||
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node.Intrinsic == Intrinsic.X86Pblendvb;
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// BLENDVPD, BLENDVPS, PBLENDVB last operand is always implied to be XMM0 when VEX is not supported.
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// SHA256RNDS2 always has an implied XMM0 as a last operand.
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if ((isBlend && !HardwareCapabilities.SupportsVexEncoding) || node.Intrinsic == Intrinsic.X86Sha256Rnds2)
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{
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Operand xmm0 = Xmm(X86Register.Xmm0, OperandType.V128);
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nodes.AddBefore(node, Operation(Instruction.Copy, xmm0, node.GetSource(2)));
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node.SetSource(2, xmm0);
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}
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break;
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}
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case Instruction.Multiply64HighSI:
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case Instruction.Multiply64HighUI:
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{
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// Handle the many restrictions of the i64 * i64 = i128 multiply instructions:
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// - The multiplicand is always in RAX.
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// - The lower 64-bits of the result is always in RAX.
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// - The higher 64-bits of the result is always in RDX.
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Operand src1 = node.GetSource(0);
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Operand rax = Gpr(X86Register.Rax, src1.Type);
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Operand rdx = Gpr(X86Register.Rdx, src1.Type);
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nodes.AddBefore(node, Operation(Instruction.Copy, rax, src1));
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node.SetSource(0, rax);
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nodes.AddAfter(node, Operation(Instruction.Copy, dest, rdx));
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node.SetDestinations(new Operand[] { rdx, rax });
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break;
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}
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case Instruction.RotateRight:
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case Instruction.ShiftLeft:
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case Instruction.ShiftRightSI:
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case Instruction.ShiftRightUI:
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{
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// The shift register is always implied to be CL (low 8-bits of RCX or ECX).
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if (node.GetSource(1).Kind == OperandKind.LocalVariable)
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{
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Operand rcx = Gpr(X86Register.Rcx, OperandType.I32);
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// The shift register is always implied to be CL (low 8-bits of RCX or ECX).
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if (node.GetSource(1).Kind == OperandKind.LocalVariable)
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{
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Operand rcx = Gpr(X86Register.Rcx, OperandType.I32);
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nodes.AddBefore(node, Operation(Instruction.Copy, rcx, node.GetSource(1)));
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nodes.AddBefore(node, Operation(Instruction.Copy, rcx, node.GetSource(1)));
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node.SetSource(1, rcx);
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node.SetSource(1, rcx);
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}
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|
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break;
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}
|
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|
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break;
|
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}
|
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}
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}
|
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|
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@ -459,7 +456,7 @@ namespace ARMeilleure.CodeGen.X86
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// Unsigned integer to FP conversions are not supported on X86.
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// We need to turn them into signed integer to FP conversions, and
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// adjust the final result.
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Operand dest = node.Destination;
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Operand dest = node.Destination;
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Operand source = node.GetSource(0);
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|
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Debug.Assert(source.Type.IsInteger(), $"Invalid source type \"{source.Type}\".");
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@ -472,8 +469,8 @@ namespace ARMeilleure.CodeGen.X86
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// and then use the 64-bits signed conversion instructions.
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Operand zex = Local(OperandType.I64);
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node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend32, zex, source));
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node = nodes.AddAfter(node, Operation(Instruction.ConvertToFP, dest, zex));
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node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend32, zex, source));
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nodes.AddAfter(node, Operation(Instruction.ConvertToFP, dest, zex));
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}
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else /* if (source.Type == OperandType.I64) */
|
||||
{
|
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@ -487,15 +484,15 @@ namespace ARMeilleure.CodeGen.X86
|
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// --- This can be done efficiently by adding the result to itself.
|
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// -- Then, we need to add the least significant bit that was shifted out.
|
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// --- We can convert the least significant bit to float, and add it to the result.
|
||||
Operand lsb = Local(OperandType.I64);
|
||||
Operand lsb = Local(OperandType.I64);
|
||||
Operand half = Local(OperandType.I64);
|
||||
|
||||
Operand lsbF = Local(dest.Type);
|
||||
|
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node = nodes.AddAfter(node, Operation(Instruction.Copy, lsb, source));
|
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node = nodes.AddAfter(node, Operation(Instruction.Copy, lsb, source));
|
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node = nodes.AddAfter(node, Operation(Instruction.Copy, half, source));
|
||||
|
||||
node = nodes.AddAfter(node, Operation(Instruction.BitwiseAnd, lsb, lsb, Const(1L)));
|
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node = nodes.AddAfter(node, Operation(Instruction.BitwiseAnd, lsb, lsb, Const(1L)));
|
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node = nodes.AddAfter(node, Operation(Instruction.ShiftRightUI, half, half, Const(1)));
|
||||
|
||||
node = nodes.AddAfter(node, Operation(Instruction.ConvertToFP, lsbF, lsb));
|
||||
@ -513,7 +510,7 @@ namespace ARMeilleure.CodeGen.X86
|
||||
// There's no SSE FP negate instruction, so we need to transform that into
|
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// a XOR of the value to be negated with a mask with the highest bit set.
|
||||
// This also produces -0 for a negation of the value 0.
|
||||
Operand dest = node.Destination;
|
||||
Operand dest = node.Destination;
|
||||
Operand source = node.GetSource(0);
|
||||
|
||||
Debug.Assert(dest.Type == OperandType.FP32 ||
|
||||
@ -569,14 +566,14 @@ namespace ARMeilleure.CodeGen.X86
|
||||
if ((index & 1) != 0)
|
||||
{
|
||||
node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend8, temp1, temp1));
|
||||
node = nodes.AddAfter(node, Operation(Instruction.ShiftLeft, temp2, temp2, Const(8)));
|
||||
node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr, temp1, temp1, temp2));
|
||||
node = nodes.AddAfter(node, Operation(Instruction.ShiftLeft, temp2, temp2, Const(8)));
|
||||
node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr, temp1, temp1, temp2));
|
||||
}
|
||||
else
|
||||
{
|
||||
node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend8, temp2, temp2));
|
||||
node = nodes.AddAfter(node, Operation(Instruction.BitwiseAnd, temp1, temp1, Const(0xff00)));
|
||||
node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr, temp1, temp1, temp2));
|
||||
node = nodes.AddAfter(node, Operation(Instruction.BitwiseAnd, temp1, temp1, Const(0xff00)));
|
||||
node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr, temp1, temp1, temp2));
|
||||
}
|
||||
|
||||
Operation vinsOp = Operation(Instruction.VectorInsert16, dest, src1, temp1, Const(index >> 1));
|
||||
@ -709,16 +706,11 @@ namespace ARMeilleure.CodeGen.X86
|
||||
|
||||
private static bool HasConstSrc1(Instruction inst)
|
||||
{
|
||||
switch (inst)
|
||||
return inst switch
|
||||
{
|
||||
case Instruction.Copy:
|
||||
case Instruction.LoadArgument:
|
||||
case Instruction.Spill:
|
||||
case Instruction.SpillArg:
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
Instruction.Copy or Instruction.LoadArgument or Instruction.Spill or Instruction.SpillArg => true,
|
||||
_ => false,
|
||||
};
|
||||
}
|
||||
|
||||
private static bool HasConstSrc2(Instruction inst)
|
||||
@ -762,15 +754,15 @@ namespace ARMeilleure.CodeGen.X86
|
||||
|
||||
case Instruction.BranchIf:
|
||||
case Instruction.Compare:
|
||||
{
|
||||
Operand comp = operation.GetSource(2);
|
||||
{
|
||||
Operand comp = operation.GetSource(2);
|
||||
|
||||
Debug.Assert(comp.Kind == OperandKind.Constant);
|
||||
Debug.Assert(comp.Kind == OperandKind.Constant);
|
||||
|
||||
var compType = (Comparison)comp.AsInt32();
|
||||
var compType = (Comparison)comp.AsInt32();
|
||||
|
||||
return compType == Comparison.Equal || compType == Comparison.NotEqual;
|
||||
}
|
||||
return compType == Comparison.Equal || compType == Comparison.NotEqual;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
@ -793,4 +785,4 @@ namespace ARMeilleure.CodeGen.X86
|
||||
return info.Type != IntrinsicType.Crc32;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user