daniel/Ryujinx
1
0
Fork 0
mirror of https://github.com/Ryujinx/Ryujinx.git synced 2025-08-08 07:32:32 -07:00
Code Issues Packages Projects Releases Wiki Activity

[ARMeilleure] Address dotnet-format issues (#5357)

Browse Source 
* dotnet format style --severity info

Some changes were manually reverted.

* dotnet format analyzers --serverity info

Some changes have been minimally adapted.

* Restore a few unused methods and variables

* Silence dotnet format IDE0060 warnings

* Silence dotnet format IDE0052 warnings

* Address or silence dotnet format IDE1006 warnings

* Address or silence dotnet format CA2208 warnings

* Address dotnet format CA1822 warnings

* Address or silence dotnet format CA1069 warnings

* Silence CA1806 and CA1834 issues

* Address dotnet format CA1401 warnings

* Fix new dotnet-format issues after rebase

* Address review comments

* Address dotnet format CA2208 warnings properly

* Fix formatting for switch expressions

* Address most dotnet format whitespace warnings

* Apply dotnet format whitespace formatting

A few of them have been manually reverted and the corresponding warning was silenced

* Add previously silenced warnings back

I have no clue how these disappeared

* Revert formatting changes for OpCodeTable.cs

* Enable formatting for a few cases again

* Format if-blocks correctly

* Enable formatting for a few more cases again

* Fix inline comment alignment

* Run dotnet format after rebase and remove unused usings

- analyzers
- style
- whitespace

* Disable 'prefer switch expression' rule

* Add comments to disabled warnings

* Remove a few unused parameters

* Adjust namespaces

* Simplify properties and array initialization, Use const when possible, Remove trailing commas

* Start working on disabled warnings

* Fix and silence a few dotnet-format warnings again

* Address IDE0251 warnings

* Address a few disabled IDE0060 warnings

* Silence IDE0060 in .editorconfig

* Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas"

This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e.

* dotnet format whitespace after rebase

* First dotnet format pass

* Remove unnecessary formatting exclusion

* Add unsafe dotnet format changes

* Change visibility of JitSupportDarwin to internal
This commit is contained in:
TSRBerry
2023-06-26 07:25:06 +02:00
committed by GitHub
parent 2de78a2d55
commit ff53dcf560
300 changed files with 3515 additions and 3120 deletions
Download Patch File Download Diff File Expand all files Collapse all files

85
src/ARMeilleure/Instructions/InstEmitSimdMove.cs
View File

@@ -3,7 +3,6 @@ using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using System.Collections.Generic;
using System.Reflection;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
@@ -12,19 +11,19 @@ namespace ARMeilleure.Instructions
{
static partial class InstEmit
{
#region "Masks"
#region "Masks"
private static readonly long[] _masksE0_Uzp = new long[]
{
13L << 56 | 09L << 48 | 05L << 40 | 01L << 32 | 12L << 24 | 08L << 16 | 04L << 8 | 00L << 0,
11L << 56 | 10L << 48 | 03L << 40 | 02L << 32 | 09L << 24 | 08L << 16 | 01L << 8 | 00L << 0
11L << 56 | 10L << 48 | 03L << 40 | 02L << 32 | 09L << 24 | 08L << 16 | 01L << 8 | 00L << 0,
};
private static readonly long[] _masksE1_Uzp = new long[]
{
15L << 56 | 11L << 48 | 07L << 40 | 03L << 32 | 14L << 24 | 10L << 16 | 06L << 8 | 02L << 0,
15L << 56 | 14L << 48 | 07L << 40 | 06L << 32 | 13L << 24 | 12L << 16 | 05L << 8 | 04L << 0
15L << 56 | 14L << 48 | 07L << 40 | 06L << 32 | 13L << 24 | 12L << 16 | 05L << 8 | 04L << 0,
};
#endregion
#endregion
public static void Dup_Gp(ArmEmitterContext context)
{
@@ -36,9 +35,17 @@ namespace ARMeilleure.Instructions
{
switch (op.Size)
{
case 0: n = context.ZeroExtend8 (n.Type, n); n = context.Multiply(n, Const(n.Type, 0x01010101)); break;
case 1: n = context.ZeroExtend16(n.Type, n); n = context.Multiply(n, Const(n.Type, 0x00010001)); break;
case 2: n = context.ZeroExtend32(n.Type, n); break;
case 0:
n = context.ZeroExtend8(n.Type, n);
n = context.Multiply(n, Const(n.Type, 0x01010101));
break;
case 1:
n = context.ZeroExtend16(n.Type, n);
n = context.Multiply(n, Const(n.Type, 0x00010001));
break;
case 2:
n = context.ZeroExtend32(n.Type, n);
break;
}
Operand res = context.VectorInsert(context.VectorZero(), n, 0);
@@ -209,7 +216,7 @@ namespace ARMeilleure.Instructions
OpCodeSimdFcond op = (OpCodeSimdFcond)context.CurrOp;
Operand lblTrue = Label();
Operand lblEnd = Label();
Operand lblEnd = Label();
Operand isTrue = InstEmitFlowHelper.GetCondTrue(context, op.Cond);
@@ -353,7 +360,7 @@ namespace ARMeilleure.Instructions
{
OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp;
Operand d = GetVec(op.Rd);
Operand d = GetVec(op.Rd);
Operand ne = EmitVectorExtractZx(context, op.Rn, op.SrcIndex, op.Size);
context.Copy(d, EmitVectorInsert(context, d, ne, op.DstIndex, op.Size));
@@ -497,8 +504,12 @@ namespace ARMeilleure.Instructions
switch (op.Size)
{
case 0: imm *= 0x01010101; break;
case 1: imm *= 0x00010001; break;
case 0:
imm *= 0x01010101;
break;
case 1:
imm *= 0x00010001;
break;
}
if (not)
@@ -543,7 +554,7 @@ namespace ARMeilleure.Instructions
Operand n = GetVec(op.Rn);
Operand mMask = context.AddIntrinsic(Intrinsic.X86Pcmpgtb, m, mask);
mMask = context.AddIntrinsic(Intrinsic.X86Por, mMask, m);
mMask = context.AddIntrinsic(Intrinsic.X86Por, mMask, m);
res = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mMask);
}
@@ -557,7 +568,7 @@ namespace ARMeilleure.Instructions
Operand mSubMask = context.AddIntrinsic(Intrinsic.X86Psubb, m, idxMask);
Operand mMask = context.AddIntrinsic(Intrinsic.X86Pcmpgtb, mSubMask, mask);
mMask = context.AddIntrinsic(Intrinsic.X86Por, mMask, mSubMask);
mMask = context.AddIntrinsic(Intrinsic.X86Por, mMask, mSubMask);
Operand res2 = context.AddIntrinsic(Intrinsic.X86Pshufb, ni, mMask);
@@ -566,7 +577,7 @@ namespace ARMeilleure.Instructions
if (!isTbl)
{
Operand idxMask = X86GetAllElements(context, (0x1010101010101010L * op.Size) - 0x0101010101010101L);
Operand idxMask = X86GetAllElements(context, (0x1010101010101010L * op.Size) - 0x0101010101010101L);
Operand zeroMask = context.VectorZero();
Operand mPosMask = context.AddIntrinsic(Intrinsic.X86Pcmpgtb, m, idxMask);
@@ -590,7 +601,7 @@ namespace ARMeilleure.Instructions
{
Operand d = GetVec(op.Rd);
List<Operand> args = new List<Operand>();
List<Operand> args = new();
if (!isTbl)
{
@@ -612,20 +623,36 @@ namespace ARMeilleure.Instructions
{
switch (op.Size)
{
case 1: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl1)); break;
case 2: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl2)); break;
case 3: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl3)); break;
case 4: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl4)); break;
case 1:
info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl1));
break;
case 2:
info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl2));
break;
case 3:
info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl3));
break;
case 4:
info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl4));
break;
}
}
else
{
switch (op.Size)
{
case 1: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx1)); break;
case 2: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx2)); break;
case 3: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx3)); break;
case 4: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx4)); break;
case 1:
info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx1));
break;
case 2:
info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx2));
break;
case 3:
info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx3));
break;
case 4:
info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx4));
break;
}
}
@@ -644,7 +671,7 @@ namespace ARMeilleure.Instructions
if (op.Size < 3)
{
long maskE0 = EvenMasks[op.Size];
long maskE1 = OddMasks [op.Size];
long maskE1 = OddMasks[op.Size];
mask = X86GetScalar(context, maskE0);
@@ -691,7 +718,7 @@ namespace ARMeilleure.Instructions
Operand ne = EmitVectorExtractZx(context, op.Rn, pairIndex + part, op.Size);
Operand me = EmitVectorExtractZx(context, op.Rm, pairIndex + part, op.Size);
res = EmitVectorInsert(context, res, ne, pairIndex, op.Size);
res = EmitVectorInsert(context, res, ne, pairIndex, op.Size);
res = EmitVectorInsert(context, res, me, pairIndex + 1, op.Size);
}
@@ -712,7 +739,7 @@ namespace ARMeilleure.Instructions
if (op.Size < 3)
{
long maskE0 = EvenMasks[op.Size];
long maskE1 = OddMasks [op.Size];
long maskE1 = OddMasks[op.Size];
mask = X86GetScalar(context, maskE0);
@@ -784,7 +811,7 @@ namespace ARMeilleure.Instructions
Operand ne = EmitVectorExtractZx(context, op.Rn, idx + part, op.Size);
Operand me = EmitVectorExtractZx(context, op.Rm, idx + part, op.Size);
res = EmitVectorInsert(context, res, ne, index, op.Size);
res = EmitVectorInsert(context, res, ne, index, op.Size);
res = EmitVectorInsert(context, res, me, pairs + index, op.Size);
}
@@ -839,7 +866,7 @@ namespace ARMeilleure.Instructions
Operand ne = EmitVectorExtractZx(context, op.Rn, baseIndex + index, op.Size);
Operand me = EmitVectorExtractZx(context, op.Rm, baseIndex + index, op.Size);
res = EmitVectorInsert(context, res, ne, pairIndex, op.Size);
res = EmitVectorInsert(context, res, ne, pairIndex, op.Size);
res = EmitVectorInsert(context, res, me, pairIndex + 1, op.Size);
}