LDj3SNuD 18f576f49d Why not a nice Span.

2021-02-09 17:00:09 +01:00

..

CodeGen

Merge branch 'master' into pptc_and_pool_enhancements

2021-02-08 03:48:40 +01:00

Common

PPTC & Pool Enhancements.

2021-01-27 06:21:37 +01:00

Decoders

Implement PRFM (register variant) as NOP (#1956)

2021-01-26 16:09:27 +11:00

Diagnostics

Implement block placement (#1549)

2020-09-19 20:00:24 -03:00

Instructions

Lower precision of estimate instruction results to match Arm behavior (#1943)

2021-01-28 10:23:00 +11:00

IntermediateRepresentation

Merge branch 'master' into pptc_and_pool_enhancements

2021-01-27 06:25:40 +01:00

Memory

Clear JIT cache on exit (#1518)

2020-12-16 17:07:42 -03:00

State

CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)

2021-01-04 23:45:54 +01:00

Translation

Why not a nice Span.

2021-02-09 17:00:09 +01:00

ARMeilleure.csproj

infra: Migrate to .NET 5 (#1694)

2020-11-15 19:27:15 +01:00

Optimizations.cs

CPU: Implement VFNMS.F32/64 (#1758)

2020-12-03 20:20:02 +01:00

Statistics.cs

Suppress warnings from fields never used or never assigned (CS0169 and CS0649) (#919)

2020-04-21 07:59:59 +10:00