daniel/Ryujinx
1
0
Fork 0
mirror of https://github.com/Ryujinx/Ryujinx.git synced 2025-01-11 10:31:56 -08:00
Code Issues Packages Projects Releases Wiki Activity
Ryujinx/Ryujinx.Tests/Cpu
History
LDj3SNuD 83d94b21d0
Add FMaxNmV & FMinNmV Inst.s with Test. (#1279) 
Successful unit testing on Windows (debug and release mode).
2020-05-27 18:51:59 +02:00
..
CpuTest32.cs
Implement a new physical memory manager and replace DeviceMemory (#856)
2020-05-04 08:54:50 +10:00
CpuTest.cs
Implement a new physical memory manager and replace DeviceMemory (#856)
2020-05-04 08:54:50 +10:00
CpuTestAlu32.cs
Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954)
2020-03-01 07:51:55 +11:00
CpuTestAlu.cs
Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696)
2019-06-12 09:03:31 -03:00
CpuTestAluBinary.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
CpuTestAluImm.cs
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
2018-11-01 01:22:09 -03:00
CpuTestAluRs32.cs
Add most of the A32 instruction set to ARMeilleure (#897)
2020-02-24 08:20:40 +11:00
CpuTestAluRs.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
CpuTestAluRx.cs
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
2018-11-01 01:22:09 -03:00
CpuTestBf32.cs
Add most of the A32 instruction set to ARMeilleure (#897)
2020-02-24 08:20:40 +11:00
CpuTestBfm.cs
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
2018-11-01 01:22:09 -03:00
CpuTestCcmpImm.cs
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
2018-11-01 01:22:09 -03:00
CpuTestCcmpReg.cs
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
2018-11-01 01:22:09 -03:00
CpuTestCsel.cs
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
2018-11-01 01:22:09 -03:00
CpuTestMisc.cs
Improve V128 (#1097)
2020-04-17 08:19:20 +10:00
CpuTestMov.cs
Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696)
2019-06-12 09:03:31 -03:00
CpuTestMul32.cs
Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954)
2020-03-01 07:51:55 +11:00
CpuTestMul.cs
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
2018-11-01 01:22:09 -03:00
CpuTestSimd.cs
Add FMaxNmV & FMinNmV Inst.s with Test. (#1279)
2020-05-27 18:51:59 +02:00
CpuTestSimdCrypto32.cs
Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (#982)
2020-03-14 10:29:58 +11:00
CpuTestSimdCrypto.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
CpuTestSimdCvt.cs
Implemented fast paths for: (#846)
2019-12-29 22:22:47 -03:00
CpuTestSimdExt.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
CpuTestSimdFcond.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
CpuTestSimdFmov.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
CpuTestSimdImm.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
CpuTestSimdIns.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
CpuTestSimdLogical32.cs
Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (#982)
2020-03-14 10:29:58 +11:00
CpuTestSimdMemory32.cs
Add most of the A32 instruction set to ARMeilleure (#897)
2020-02-24 08:20:40 +11:00
CpuTestSimdMov32.cs
Implement VMOVL and VORR.I32 AArch32 SIMD instructions (#960)
2020-03-10 16:17:30 +11:00
CpuTestSimdReg32.cs
Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other fixes (#977)
2020-03-11 11:49:27 +11:00
CpuTestSimdReg.cs
Implement FACGE and FACGT (Scalar and Vector) AArch64 SIMD instructions (#956)
2020-03-01 07:51:17 +11:00
CpuTestSimdRegElem32.cs
Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other fixes (#977)
2020-03-11 11:49:27 +11:00
CpuTestSimdRegElem.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
CpuTestSimdRegElemF.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
CpuTestSimdShImm32.cs
Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other fixes (#977)
2020-03-11 11:49:27 +11:00
CpuTestSimdShImm.cs
Implemented fast paths for: (#846)
2019-12-29 22:22:47 -03:00
CpuTestSimdTbl.cs
Add Tbx Inst. (fast & slow paths), with Tests. (#782)
2019-10-04 11:43:20 -03:00
CpuTestSystem.cs
Add Mrs & Msr (Nzcv) Inst., with Tests. (#819)
2019-11-14 13:08:07 +11:00