mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-12-26 05:51:21 -08:00
22b2cb39af
* Turn `MemoryOperand` into a struct
* Remove `IntrinsicOperation`
* Remove `PhiNode`
* Remove `Node`
* Turn `Operand` into a struct
* Turn `Operation` into a struct
* Clean up pool management methods
* Add `Arena` allocator
* Move `OperationHelper` to `Operation.Factory`
* Move `OperandHelper` to `Operand.Factory`
* Optimize `Operation` a bit
* Fix `Arena` initialization
* Rename `NativeList<T>` to `ArenaList<T>`
* Reduce `Operand` size from 88 to 56 bytes
* Reduce `Operation` size from 56 to 40 bytes
* Add optimistic interning of Register & Constant operands
* Optimize `RegisterUsage` pass a bit
* Optimize `RemoveUnusedNodes` pass a bit
Iterating in reverse-order allows killing dependency chains in a single
pass.
* Fix PPTC symbols
* Optimize `BasicBlock` a bit
Reduce allocations from `_successor` & `DominanceFrontiers`
* Fix `Operation` resize
* Make `Arena` expandable
Change the arena allocator to be expandable by allocating in pages, with
some of them being pooled. Currently 32 pages are pooled. An LRU removal
mechanism should probably be added to it.
Apparently MHR can allocate bitmaps large enough to exceed the 16MB
limit for the type.
* Move `Arena` & `ArenaList` to `Common`
* Remove `ThreadStaticPool` & co
* Add `PhiOperation`
* Reduce `Operand` size from 56 from 48 bytes
* Add linear-probing to `Operand` intern table
* Optimize `HybridAllocator` a bit
* Add `Allocators` class
* Tune `ArenaAllocator` sizes
* Add page removal mechanism to `ArenaAllocator`
Remove pages which have not been used for more than 5s after each reset.
I am on fence if this would be better using a Gen2 callback object like
the one in System.Buffers.ArrayPool<T>, to trim the pool. Because right
now if a large translation happens, the pages will be freed only after a
reset. This reset may not happen for a while because no new translation
is hit, but the arena base sizes are rather small.
* Fix `OOM` when allocating larger than page size in `ArenaAllocator`
Tweak resizing mechanism for Operand.Uses and Assignemnts.
* Optimize `Optimizer` a bit
* Optimize `Operand.Add<T>/Remove<T>` a bit
* Clean up `PreAllocator`
* Fix phi insertion order
Reduce codegen diffs.
* Fix code alignment
* Use new heuristics for degree of parallelism
* Suppress warnings
* Address gdkchan's feedback
Renamed `GetValue()` to `GetValueUnsafe()` to make it more clear that
`Operand.Value` should usually not be modified directly.
* Add fast path to `ArenaAllocator`
* Assembly for `ArenaAllocator.Allocate(ulong)`:
.L0:
mov rax, [rcx+0x18]
lea r8, [rax+rdx]
cmp r8, [rcx+0x10]
ja short .L2
.L1:
mov rdx, [rcx+8]
add rax, [rdx+8]
mov [rcx+0x18], r8
ret
.L2:
jmp ArenaAllocator.AllocateSlow(UInt64)
A few variable/field had to be changed to ulong so that RyuJIT avoids
emitting zero-extends.
* Implement a new heuristic to free pooled pages.
If an arena is used often, it is more likely that its pages will be
needed, so the pages are kept for longer (e.g: during PPTC rebuild or
burst sof compilations). If is not used often, then it is more likely
that its pages will not be needed (e.g: after PPTC rebuild or bursts
of compilations).
* Address riperiperi's feedback
* Use `EqualityComparer<T>` in `IntrusiveList<T>`
Avoids a potential GC hole in `Equals(T, T)`.
294 lines
10 KiB
C#
294 lines
10 KiB
C#
using ARMeilleure.Decoders;
|
|
using ARMeilleure.IntermediateRepresentation;
|
|
using ARMeilleure.State;
|
|
using ARMeilleure.Translation;
|
|
using System;
|
|
using System.Reflection;
|
|
|
|
using static ARMeilleure.Instructions.InstEmitHelper;
|
|
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
|
|
|
|
namespace ARMeilleure.Instructions
|
|
{
|
|
static partial class InstEmit32
|
|
{
|
|
public static void Mcr(ArmEmitterContext context)
|
|
{
|
|
OpCode32System op = (OpCode32System)context.CurrOp;
|
|
|
|
if (op.Coproc != 15)
|
|
{
|
|
InstEmit.Und(context);
|
|
|
|
return;
|
|
}
|
|
|
|
if (op.Opc1 != 0)
|
|
{
|
|
throw new NotImplementedException($"Unknown MRC Opc1 0x{op.Opc1:X16} at 0x{op.Address:X16}.");
|
|
}
|
|
|
|
MethodInfo info;
|
|
|
|
switch (op.CRn)
|
|
{
|
|
case 13: // Process and Thread Info.
|
|
if (op.CRm != 0)
|
|
{
|
|
throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X16} at 0x{op.Address:X16}.");
|
|
}
|
|
|
|
switch (op.Opc2)
|
|
{
|
|
case 2:
|
|
info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetTpidrEl032)); break;
|
|
|
|
default:
|
|
throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X16} at 0x{op.Address:X16}.");
|
|
}
|
|
|
|
break;
|
|
|
|
case 7:
|
|
switch (op.CRm) // Cache and Memory barrier.
|
|
{
|
|
case 10:
|
|
switch (op.Opc2)
|
|
{
|
|
case 5: // Data Memory Barrier Register.
|
|
return; // No-op.
|
|
|
|
default:
|
|
throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X16} at 0x{op.Address:X16}.");
|
|
}
|
|
|
|
default:
|
|
throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X16} at 0x{op.Address:X16}.");
|
|
}
|
|
|
|
default:
|
|
throw new NotImplementedException($"Unknown MRC 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
|
|
}
|
|
|
|
context.Call(info, GetIntA32(context, op.Rt));
|
|
}
|
|
|
|
public static void Mrc(ArmEmitterContext context)
|
|
{
|
|
OpCode32System op = (OpCode32System)context.CurrOp;
|
|
|
|
if (op.Coproc != 15)
|
|
{
|
|
InstEmit.Und(context);
|
|
|
|
return;
|
|
}
|
|
|
|
if (op.Opc1 != 0)
|
|
{
|
|
throw new NotImplementedException($"Unknown MRC Opc1 0x{op.Opc1:X16} at 0x{op.Address:X16}.");
|
|
}
|
|
|
|
MethodInfo info;
|
|
|
|
switch (op.CRn)
|
|
{
|
|
case 13: // Process and Thread Info.
|
|
if (op.CRm != 0)
|
|
{
|
|
throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X16} at 0x{op.Address:X16}.");
|
|
}
|
|
|
|
switch (op.Opc2)
|
|
{
|
|
case 2:
|
|
info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetTpidrEl032)); break;
|
|
|
|
case 3:
|
|
info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetTpidr32)); break;
|
|
|
|
default:
|
|
throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X16} at 0x{op.Address:X16}.");
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
throw new NotImplementedException($"Unknown MRC 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
|
|
}
|
|
|
|
if (op.Rt == RegisterAlias.Aarch32Pc)
|
|
{
|
|
// Special behavior: copy NZCV flags into APSR.
|
|
EmitSetNzcv(context, context.Call(info));
|
|
|
|
return;
|
|
}
|
|
else
|
|
{
|
|
SetIntA32(context, op.Rt, context.Call(info));
|
|
}
|
|
}
|
|
|
|
public static void Mrrc(ArmEmitterContext context)
|
|
{
|
|
OpCode32System op = (OpCode32System)context.CurrOp;
|
|
|
|
if (op.Coproc != 15)
|
|
{
|
|
InstEmit.Und(context);
|
|
|
|
return;
|
|
}
|
|
|
|
int opc = op.MrrcOp;
|
|
|
|
MethodInfo info;
|
|
|
|
switch (op.CRm)
|
|
{
|
|
case 14: // Timer.
|
|
switch (opc)
|
|
{
|
|
case 0:
|
|
info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntpctEl0)); break;
|
|
|
|
default:
|
|
throw new NotImplementedException($"Unknown MRRC Opc1 0x{opc:X16} at 0x{op.Address:X16}.");
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
throw new NotImplementedException($"Unknown MRRC 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
|
|
}
|
|
|
|
Operand result = context.Call(info);
|
|
|
|
SetIntA32(context, op.Rt, context.ConvertI64ToI32(result));
|
|
SetIntA32(context, op.CRn, context.ConvertI64ToI32(context.ShiftRightUI(result, Const(32))));
|
|
}
|
|
|
|
public static void Nop(ArmEmitterContext context) { }
|
|
|
|
public static void Vmrs(ArmEmitterContext context)
|
|
{
|
|
OpCode32SimdSpecial op = (OpCode32SimdSpecial)context.CurrOp;
|
|
|
|
if (op.Rt == RegisterAlias.Aarch32Pc && op.Sreg == 0b0001)
|
|
{
|
|
// Special behavior: copy NZCV flags into APSR.
|
|
SetFlag(context, PState.VFlag, GetFpFlag(FPState.VFlag));
|
|
SetFlag(context, PState.CFlag, GetFpFlag(FPState.CFlag));
|
|
SetFlag(context, PState.ZFlag, GetFpFlag(FPState.ZFlag));
|
|
SetFlag(context, PState.NFlag, GetFpFlag(FPState.NFlag));
|
|
|
|
return;
|
|
}
|
|
|
|
switch (op.Sreg)
|
|
{
|
|
case 0b0000: // FPSID
|
|
throw new NotImplementedException("Supervisor Only");
|
|
case 0b0001: // FPSCR
|
|
EmitGetFpscr(context); return;
|
|
case 0b0101: // MVFR2
|
|
throw new NotImplementedException("MVFR2");
|
|
case 0b0110: // MVFR1
|
|
throw new NotImplementedException("MVFR1");
|
|
case 0b0111: // MVFR0
|
|
throw new NotImplementedException("MVFR0");
|
|
case 0b1000: // FPEXC
|
|
throw new NotImplementedException("Supervisor Only");
|
|
default:
|
|
throw new NotImplementedException($"Unknown VMRS 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
|
|
}
|
|
}
|
|
|
|
public static void Vmsr(ArmEmitterContext context)
|
|
{
|
|
OpCode32SimdSpecial op = (OpCode32SimdSpecial)context.CurrOp;
|
|
|
|
switch (op.Sreg)
|
|
{
|
|
case 0b0000: // FPSID
|
|
throw new NotImplementedException("Supervisor Only");
|
|
case 0b0001: // FPSCR
|
|
EmitSetFpscr(context); return;
|
|
case 0b0101: // MVFR2
|
|
throw new NotImplementedException("MVFR2");
|
|
case 0b0110: // MVFR1
|
|
throw new NotImplementedException("MVFR1");
|
|
case 0b0111: // MVFR0
|
|
throw new NotImplementedException("MVFR0");
|
|
case 0b1000: // FPEXC
|
|
throw new NotImplementedException("Supervisor Only");
|
|
default:
|
|
throw new NotImplementedException($"Unknown VMSR 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
|
|
}
|
|
}
|
|
|
|
private static void EmitSetNzcv(ArmEmitterContext context, Operand t)
|
|
{
|
|
Operand v = context.ShiftRightUI(t, Const((int)PState.VFlag));
|
|
v = context.BitwiseAnd(v, Const(1));
|
|
|
|
Operand c = context.ShiftRightUI(t, Const((int)PState.CFlag));
|
|
c = context.BitwiseAnd(c, Const(1));
|
|
|
|
Operand z = context.ShiftRightUI(t, Const((int)PState.ZFlag));
|
|
z = context.BitwiseAnd(z, Const(1));
|
|
|
|
Operand n = context.ShiftRightUI(t, Const((int)PState.NFlag));
|
|
n = context.BitwiseAnd(n, Const(1));
|
|
|
|
SetFlag(context, PState.VFlag, v);
|
|
SetFlag(context, PState.CFlag, c);
|
|
SetFlag(context, PState.ZFlag, z);
|
|
SetFlag(context, PState.NFlag, n);
|
|
}
|
|
|
|
private static void EmitGetFpscr(ArmEmitterContext context)
|
|
{
|
|
OpCode32SimdSpecial op = (OpCode32SimdSpecial)context.CurrOp;
|
|
|
|
Operand vSh = context.ShiftLeft(GetFpFlag(FPState.VFlag), Const((int)FPState.VFlag));
|
|
Operand cSh = context.ShiftLeft(GetFpFlag(FPState.CFlag), Const((int)FPState.CFlag));
|
|
Operand zSh = context.ShiftLeft(GetFpFlag(FPState.ZFlag), Const((int)FPState.ZFlag));
|
|
Operand nSh = context.ShiftLeft(GetFpFlag(FPState.NFlag), Const((int)FPState.NFlag));
|
|
|
|
Operand nzcvSh = context.BitwiseOr(context.BitwiseOr(nSh, zSh), context.BitwiseOr(cSh, vSh));
|
|
|
|
Operand fpscr = context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpscr)));
|
|
|
|
SetIntA32(context, op.Rt, context.BitwiseOr(nzcvSh, fpscr));
|
|
}
|
|
|
|
private static void EmitSetFpscr(ArmEmitterContext context)
|
|
{
|
|
OpCode32SimdSpecial op = (OpCode32SimdSpecial)context.CurrOp;
|
|
|
|
Operand t = GetIntA32(context, op.Rt);
|
|
|
|
Operand v = context.ShiftRightUI(t, Const((int)FPState.VFlag));
|
|
v = context.BitwiseAnd(v, Const(1));
|
|
|
|
Operand c = context.ShiftRightUI(t, Const((int)FPState.CFlag));
|
|
c = context.BitwiseAnd(c, Const(1));
|
|
|
|
Operand z = context.ShiftRightUI(t, Const((int)FPState.ZFlag));
|
|
z = context.BitwiseAnd(z, Const(1));
|
|
|
|
Operand n = context.ShiftRightUI(t, Const((int)FPState.NFlag));
|
|
n = context.BitwiseAnd(n, Const(1));
|
|
|
|
SetFpFlag(context, FPState.VFlag, v);
|
|
SetFpFlag(context, FPState.CFlag, c);
|
|
SetFpFlag(context, FPState.ZFlag, z);
|
|
SetFpFlag(context, FPState.NFlag, n);
|
|
|
|
context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpscr)), t);
|
|
}
|
|
}
|
|
}
|