mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-12-29 11:41:22 -08:00
2f16491712
* Get rid of Reflection.Emit dependency on CPU and Shader projects * Remove useless private sets * Missed those due to the alignment
39 lines
1.2 KiB
C#
39 lines
1.2 KiB
C#
namespace ARMeilleure.Decoders
|
|
{
|
|
class OpCode32SimdImm44 : OpCode32, IOpCode32SimdImm
|
|
{
|
|
public int Vd { get; }
|
|
public long Immediate { get; }
|
|
public int Size { get; }
|
|
public int Elems { get; }
|
|
|
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm44(inst, address, opCode);
|
|
|
|
public OpCode32SimdImm44(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
|
{
|
|
Size = (opCode >> 8) & 0x3;
|
|
|
|
bool single = Size != 3;
|
|
|
|
if (single)
|
|
{
|
|
Vd = ((opCode >> 22) & 0x1) | ((opCode >> 11) & 0x1e);
|
|
}
|
|
else
|
|
{
|
|
Vd = ((opCode >> 18) & 0x10) | ((opCode >> 12) & 0xf);
|
|
}
|
|
|
|
long imm;
|
|
|
|
imm = ((uint)opCode >> 0) & 0xf;
|
|
imm |= ((uint)opCode >> 12) & 0xf0;
|
|
|
|
Immediate = (Size == 3) ? (long)DecoderHelper.Imm8ToFP64Table[(int)imm] : DecoderHelper.Imm8ToFP32Table[(int)imm];
|
|
|
|
RegisterSize = (!single) ? RegisterSize.Int64 : RegisterSize.Int32;
|
|
Elems = 1;
|
|
}
|
|
}
|
|
}
|