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Ryujinx/Ryujinx.Tests/Cpu
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gdkchan 219f63ff4e
Fix CPU FCVTN instruction implementation (slow path) (#4159) 
* Fix CPU FCVTN instruction implementation (slow path)

* PPTC version bump
2022-12-21 23:05:58 +00:00
..
CpuContext.cs
Refactor CPU interface to allow the implementation of other CPU emulators (#3362)
2022-05-31 16:29:35 -03:00
CpuTest32.cs
Use upstream unicorn for Ryujinx.Tests.Unicorn (#3771)
2022-11-20 20:18:21 +01:00
CpuTest.cs
Use upstream unicorn for Ryujinx.Tests.Unicorn (#3771)
2022-11-20 20:18:21 +01:00
CpuTestAlu32.cs
Implement PLD and SUB (imm16) on T32, plus UADD8, SADD8, USUB8 and SSUB8 on both A32 and T32 (#3693)
2022-09-13 19:51:40 -03:00
CpuTestAlu.cs
Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696)
2019-06-12 09:03:31 -03:00
CpuTestAluBinary32.cs
Removed unused usings. (#3593)
2022-08-18 18:04:54 +02:00
CpuTestAluBinary.cs
Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)
2020-07-13 20:48:14 +10:00
CpuTestAluImm32.cs
Removed unused usings. (#3593)
2022-08-18 18:04:54 +02:00
CpuTestAluImm.cs
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
2018-11-01 01:22:09 -03:00
CpuTestAluRs32.cs
Add most of the A32 instruction set to ARMeilleure (#897)
2020-02-24 08:20:40 +11:00
CpuTestAluRs.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
CpuTestAluRx.cs
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
2018-11-01 01:22:09 -03:00
CpuTestBf32.cs
Add most of the A32 instruction set to ARMeilleure (#897)
2020-02-24 08:20:40 +11:00
CpuTestBfm.cs
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
2018-11-01 01:22:09 -03:00
CpuTestCcmpImm.cs
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
2018-11-01 01:22:09 -03:00
CpuTestCcmpReg.cs
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
2018-11-01 01:22:09 -03:00
CpuTestCsel.cs
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
2018-11-01 01:22:09 -03:00
CpuTestMisc32.cs
CPU: This PR fixes Fpscr, among other things. (#1433)
2020-08-08 17:18:51 +02:00
CpuTestMisc.cs
Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335)
2020-07-13 21:08:47 +10:00
CpuTestMov.cs
Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696)
2019-06-12 09:03:31 -03:00
CpuTestMul32.cs
Removed unused usings. (#3593)
2022-08-18 18:04:54 +02:00
CpuTestMul.cs
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
2018-11-01 01:22:09 -03:00
CpuTestSimd32.cs
Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
2022-09-09 21:47:38 -03:00
CpuTestSimd.cs
Fix CPU FCVTN instruction implementation (slow path) (#4159)
2022-12-21 23:05:58 +00:00
CpuTestSimdCrypto32.cs
Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (#982)
2020-03-14 10:29:58 +11:00
CpuTestSimdCrypto.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
CpuTestSimdCvt32.cs
A32: Implement VCVTT, VCVTB (#3710)
2022-10-19 02:36:04 +02:00
CpuTestSimdCvt.cs
Implement FCVTNS (Scalar GP) (#2953)
2022-01-19 22:21:44 -03:00
CpuTestSimdExt.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
CpuTestSimdFcond.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
CpuTestSimdFmov.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
CpuTestSimdImm.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
CpuTestSimdIns.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
CpuTestSimdLogical32.cs
Removed unused usings. (#3593)
2022-08-18 18:04:54 +02:00
CpuTestSimdMemory32.cs
Fix increment on Arm32 NEON VLDn/VSTn instructions with regs > 1 (#3695)
2022-09-13 08:24:09 +02:00
CpuTestSimdMov32.cs
Removed unused usings. (#3593)
2022-08-18 18:04:54 +02:00
CpuTestSimdReg32.cs
Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
2022-09-09 21:47:38 -03:00
CpuTestSimdReg.cs
CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)
2021-01-04 23:45:54 +01:00
CpuTestSimdRegElem32.cs
Removed unused usings. (#3593)
2022-08-18 18:04:54 +02:00
CpuTestSimdRegElem.cs
Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139)
2021-03-25 23:33:32 +01:00
CpuTestSimdRegElemF.cs
Add a new JIT compiler for CPU code (#693)
2019-08-08 21:56:22 +03:00
CpuTestSimdShImm32.cs
Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
2022-09-09 21:47:38 -03:00
CpuTestSimdShImm.cs
CPU (A64): Add Scvtf_S_Fixed & Ucvtf_S_Fixed with Tests. (#1492)
2020-08-31 20:48:21 -03:00
CpuTestSimdTbl.cs
Add Tbx Inst. (fast & slow paths), with Tests. (#782)
2019-10-04 11:43:20 -03:00
CpuTestSystem.cs
Add Mrs & Msr (Nzcv) Inst., with Tests. (#819)
2019-11-14 13:08:07 +11:00
CpuTestT32Alu.cs
Removed unused usings. (#3593)
2022-08-18 18:04:54 +02:00
CpuTestT32Flow.cs
T32: Implement B, B.cond, BL, BLX (#3155)
2022-03-04 23:05:08 +01:00
CpuTestT32Mem.cs
Removed unused usings. (#3593)
2022-08-18 18:04:54 +02:00
CpuTestThumb.cs
Removed unused usings. (#3593)
2022-08-18 18:04:54 +02:00
PrecomputedMemoryThumbTestCase.cs
Removed unused usings. (#3593)
2022-08-18 18:04:54 +02:00
PrecomputedThumbTestCase.cs
T32: Implement ALU (shifted register) instructions (#3135)
2022-02-22 19:11:28 -03:00