2015-05-12 18:38:29 -07:00
|
|
|
// Copyright 2014 Citra Emulator Project
|
|
|
|
// Licensed under GPLv2 or any later version
|
|
|
|
// Refer to the license.txt file included.
|
|
|
|
|
|
|
|
#pragma once
|
|
|
|
|
2016-11-24 11:42:32 -08:00
|
|
|
#include <array>
|
2015-06-21 05:12:49 -07:00
|
|
|
#include <cstddef>
|
2017-10-09 20:56:20 -07:00
|
|
|
#include <map>
|
2016-06-27 10:42:42 -07:00
|
|
|
#include <string>
|
2018-01-27 07:16:39 -08:00
|
|
|
#include <tuple>
|
2017-07-21 19:17:57 -07:00
|
|
|
#include <vector>
|
2018-01-27 07:16:39 -08:00
|
|
|
#include <boost/icl/interval_map.hpp>
|
2017-06-21 20:21:49 -07:00
|
|
|
#include <boost/optional.hpp>
|
2015-05-12 18:38:29 -07:00
|
|
|
#include "common/common_types.h"
|
2018-01-27 07:16:39 -08:00
|
|
|
#include "core/memory_hook.h"
|
2018-04-23 21:19:36 -07:00
|
|
|
#include "video_core/memory_manager.h"
|
2015-05-12 18:38:29 -07:00
|
|
|
|
2017-09-26 15:27:44 -07:00
|
|
|
namespace Kernel {
|
|
|
|
class Process;
|
|
|
|
}
|
2015-05-12 18:38:29 -07:00
|
|
|
|
|
|
|
namespace Memory {
|
|
|
|
|
2015-05-12 19:38:56 -07:00
|
|
|
/**
|
|
|
|
* Page size used by the ARM architecture. This is the smallest granularity with which memory can
|
|
|
|
* be mapped.
|
|
|
|
*/
|
2018-02-12 13:53:32 -08:00
|
|
|
constexpr size_t PAGE_BITS = 12;
|
|
|
|
constexpr u64 PAGE_SIZE = 1 << PAGE_BITS;
|
|
|
|
constexpr u64 PAGE_MASK = PAGE_SIZE - 1;
|
|
|
|
constexpr size_t ADDRESS_SPACE_BITS = 36;
|
|
|
|
constexpr size_t PAGE_TABLE_NUM_ENTRIES = 1ULL << (ADDRESS_SPACE_BITS - PAGE_BITS);
|
2015-05-12 18:38:29 -07:00
|
|
|
|
2018-01-27 07:16:39 -08:00
|
|
|
enum class PageType : u8 {
|
2017-07-21 19:17:57 -07:00
|
|
|
/// Page is unmapped and should cause an access error.
|
|
|
|
Unmapped,
|
|
|
|
/// Page is mapped to regular memory. This is the only type you can get pointers to.
|
|
|
|
Memory,
|
2018-03-22 19:56:41 -07:00
|
|
|
/// Page is mapped to regular memory, but also needs to check for rasterizer cache flushing and
|
|
|
|
/// invalidation
|
|
|
|
RasterizerCachedMemory,
|
|
|
|
/// Page is mapped to a I/O region. Writing and reading to this page is handled by functions.
|
2017-07-21 19:17:57 -07:00
|
|
|
Special,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct SpecialRegion {
|
2018-01-27 07:16:39 -08:00
|
|
|
enum class Type {
|
|
|
|
DebugHook,
|
|
|
|
IODevice,
|
|
|
|
} type;
|
|
|
|
|
|
|
|
MemoryHookPointer handler;
|
|
|
|
|
|
|
|
bool operator<(const SpecialRegion& other) const {
|
|
|
|
return std::tie(type, handler) < std::tie(other.type, other.handler);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool operator==(const SpecialRegion& other) const {
|
|
|
|
return std::tie(type, handler) == std::tie(other.type, other.handler);
|
|
|
|
}
|
2017-07-21 19:17:57 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* A (reasonably) fast way of allowing switchable and remappable process address spaces. It loosely
|
2018-01-27 07:16:39 -08:00
|
|
|
* mimics the way a real CPU page table works.
|
2017-07-21 19:17:57 -07:00
|
|
|
*/
|
|
|
|
struct PageTable {
|
|
|
|
/**
|
|
|
|
* Array of memory pointers backing each page. An entry can only be non-null if the
|
|
|
|
* corresponding entry in the `attributes` array is of type `Memory`.
|
|
|
|
*/
|
|
|
|
std::array<u8*, PAGE_TABLE_NUM_ENTRIES> pointers;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Contains MMIO handlers that back memory regions whose entries in the `attribute` array is of
|
|
|
|
* type `Special`.
|
|
|
|
*/
|
2018-01-27 07:16:39 -08:00
|
|
|
boost::icl::interval_map<VAddr, std::set<SpecialRegion>> special_regions;
|
2017-07-21 19:17:57 -07:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Array of fine grained page attributes. If it is set to any value other than `Memory`, then
|
|
|
|
* the corresponding entry in `pointers` MUST be set to null.
|
|
|
|
*/
|
|
|
|
std::array<PageType, PAGE_TABLE_NUM_ENTRIES> attributes;
|
|
|
|
};
|
2015-05-12 18:38:29 -07:00
|
|
|
|
|
|
|
/// Physical memory regions as seen from the ARM11
|
|
|
|
enum : PAddr {
|
|
|
|
/// IO register area
|
2016-09-17 17:38:01 -07:00
|
|
|
IO_AREA_PADDR = 0x10100000,
|
|
|
|
IO_AREA_SIZE = 0x01000000, ///< IO area size (16MB)
|
2015-05-12 18:38:29 -07:00
|
|
|
IO_AREA_PADDR_END = IO_AREA_PADDR + IO_AREA_SIZE,
|
|
|
|
|
|
|
|
/// MPCore internal memory region
|
2016-09-17 17:38:01 -07:00
|
|
|
MPCORE_RAM_PADDR = 0x17E00000,
|
|
|
|
MPCORE_RAM_SIZE = 0x00002000, ///< MPCore internal memory size (8KB)
|
2015-05-12 18:38:29 -07:00
|
|
|
MPCORE_RAM_PADDR_END = MPCORE_RAM_PADDR + MPCORE_RAM_SIZE,
|
|
|
|
|
|
|
|
/// Video memory
|
2016-09-17 17:38:01 -07:00
|
|
|
VRAM_PADDR = 0x18000000,
|
|
|
|
VRAM_SIZE = 0x00600000, ///< VRAM size (6MB)
|
2015-05-12 18:38:29 -07:00
|
|
|
VRAM_PADDR_END = VRAM_PADDR + VRAM_SIZE,
|
|
|
|
|
|
|
|
/// DSP memory
|
2016-09-17 17:38:01 -07:00
|
|
|
DSP_RAM_PADDR = 0x1FF00000,
|
|
|
|
DSP_RAM_SIZE = 0x00080000, ///< DSP memory size (512KB)
|
2015-05-12 18:38:29 -07:00
|
|
|
DSP_RAM_PADDR_END = DSP_RAM_PADDR + DSP_RAM_SIZE,
|
|
|
|
|
|
|
|
/// AXI WRAM
|
2016-09-17 17:38:01 -07:00
|
|
|
AXI_WRAM_PADDR = 0x1FF80000,
|
|
|
|
AXI_WRAM_SIZE = 0x00080000, ///< AXI WRAM size (512KB)
|
2015-05-12 18:38:29 -07:00
|
|
|
AXI_WRAM_PADDR_END = AXI_WRAM_PADDR + AXI_WRAM_SIZE,
|
|
|
|
|
|
|
|
/// Main FCRAM
|
2016-09-17 17:38:01 -07:00
|
|
|
FCRAM_PADDR = 0x20000000,
|
2017-06-18 18:39:17 -07:00
|
|
|
FCRAM_SIZE = 0x08000000, ///< FCRAM size on the Old 3DS (128MB)
|
|
|
|
FCRAM_N3DS_SIZE = 0x10000000, ///< FCRAM size on the New 3DS (256MB)
|
2015-05-12 18:38:29 -07:00
|
|
|
FCRAM_PADDR_END = FCRAM_PADDR + FCRAM_SIZE,
|
|
|
|
};
|
|
|
|
|
|
|
|
/// Virtual user-space memory regions
|
|
|
|
enum : VAddr {
|
|
|
|
/// Where the application text, data and bss reside.
|
2017-10-09 18:39:32 -07:00
|
|
|
PROCESS_IMAGE_VADDR = 0x08000000,
|
|
|
|
PROCESS_IMAGE_MAX_SIZE = 0x08000000,
|
2015-05-12 18:38:29 -07:00
|
|
|
PROCESS_IMAGE_VADDR_END = PROCESS_IMAGE_VADDR + PROCESS_IMAGE_MAX_SIZE,
|
|
|
|
|
2016-09-17 17:38:01 -07:00
|
|
|
/// Maps 1:1 to an offset in FCRAM. Used for HW allocations that need to be linear in physical
|
|
|
|
/// memory.
|
|
|
|
LINEAR_HEAP_VADDR = 0x14000000,
|
|
|
|
LINEAR_HEAP_SIZE = 0x08000000,
|
2015-05-12 18:38:29 -07:00
|
|
|
LINEAR_HEAP_VADDR_END = LINEAR_HEAP_VADDR + LINEAR_HEAP_SIZE,
|
|
|
|
|
|
|
|
/// Maps 1:1 to the IO register area.
|
2016-09-17 17:38:01 -07:00
|
|
|
IO_AREA_VADDR = 0x1EC00000,
|
2015-05-12 18:38:29 -07:00
|
|
|
IO_AREA_VADDR_END = IO_AREA_VADDR + IO_AREA_SIZE,
|
|
|
|
|
|
|
|
/// Maps 1:1 to VRAM.
|
2016-09-17 17:38:01 -07:00
|
|
|
VRAM_VADDR = 0x1F000000,
|
2015-05-12 18:38:29 -07:00
|
|
|
VRAM_VADDR_END = VRAM_VADDR + VRAM_SIZE,
|
|
|
|
|
|
|
|
/// Maps 1:1 to DSP memory.
|
2016-09-17 17:38:01 -07:00
|
|
|
DSP_RAM_VADDR = 0x1FF00000,
|
2015-05-12 18:38:29 -07:00
|
|
|
DSP_RAM_VADDR_END = DSP_RAM_VADDR + DSP_RAM_SIZE,
|
|
|
|
|
|
|
|
/// Read-only page containing kernel and system configuration values.
|
2016-09-17 17:38:01 -07:00
|
|
|
CONFIG_MEMORY_VADDR = 0x1FF80000,
|
|
|
|
CONFIG_MEMORY_SIZE = 0x00001000,
|
2015-05-12 18:38:29 -07:00
|
|
|
CONFIG_MEMORY_VADDR_END = CONFIG_MEMORY_VADDR + CONFIG_MEMORY_SIZE,
|
|
|
|
|
|
|
|
/// Usually read-only page containing mostly values read from hardware.
|
2016-09-17 17:38:01 -07:00
|
|
|
SHARED_PAGE_VADDR = 0x1FF81000,
|
|
|
|
SHARED_PAGE_SIZE = 0x00001000,
|
2015-05-12 18:38:29 -07:00
|
|
|
SHARED_PAGE_VADDR_END = SHARED_PAGE_VADDR + SHARED_PAGE_SIZE,
|
|
|
|
|
2015-08-05 17:26:52 -07:00
|
|
|
/// Equivalent to LINEAR_HEAP_VADDR, but expanded to cover the extra memory in the New 3DS.
|
2016-09-17 17:38:01 -07:00
|
|
|
NEW_LINEAR_HEAP_VADDR = 0x30000000,
|
|
|
|
NEW_LINEAR_HEAP_SIZE = 0x10000000,
|
2015-08-05 17:26:52 -07:00
|
|
|
NEW_LINEAR_HEAP_VADDR_END = NEW_LINEAR_HEAP_VADDR + NEW_LINEAR_HEAP_SIZE,
|
2018-03-14 19:06:57 -07:00
|
|
|
|
|
|
|
/// Area where TLS (Thread-Local Storage) buffers are allocated.
|
|
|
|
TLS_AREA_VADDR = NEW_LINEAR_HEAP_VADDR_END,
|
|
|
|
TLS_ENTRY_SIZE = 0x200,
|
|
|
|
TLS_AREA_SIZE = 0x10000000,
|
2018-03-31 12:03:28 -07:00
|
|
|
TLS_AREA_VADDR_END = TLS_AREA_VADDR + TLS_AREA_SIZE,
|
2018-03-14 19:06:57 -07:00
|
|
|
|
|
|
|
/// Application stack
|
2018-03-31 12:03:28 -07:00
|
|
|
STACK_AREA_VADDR = TLS_AREA_VADDR_END,
|
|
|
|
STACK_AREA_SIZE = 0x10000000,
|
|
|
|
STACK_AREA_VADDR_END = STACK_AREA_VADDR + STACK_AREA_SIZE,
|
|
|
|
DEFAULT_STACK_SIZE = 0x100000,
|
2018-03-14 19:06:57 -07:00
|
|
|
|
|
|
|
/// Application heap
|
|
|
|
/// Size is confirmed to be a static value on fw 3.0.0
|
|
|
|
HEAP_VADDR = 0x108000000,
|
|
|
|
HEAP_SIZE = 0x180000000,
|
|
|
|
HEAP_VADDR_END = HEAP_VADDR + HEAP_SIZE,
|
|
|
|
|
|
|
|
/// New map region
|
|
|
|
/// Size is confirmed to be a static value on fw 3.0.0
|
|
|
|
NEW_MAP_REGION_VADDR = HEAP_VADDR_END,
|
|
|
|
NEW_MAP_REGION_SIZE = 0x80000000,
|
|
|
|
NEW_MAP_REGION_VADDR_END = NEW_MAP_REGION_VADDR + NEW_MAP_REGION_SIZE,
|
|
|
|
|
|
|
|
/// Map region
|
|
|
|
/// Size is confirmed to be a static value on fw 3.0.0
|
|
|
|
MAP_REGION_VADDR = NEW_MAP_REGION_VADDR_END,
|
|
|
|
MAP_REGION_SIZE = 0x1000000000,
|
|
|
|
MAP_REGION_VADDR_END = MAP_REGION_VADDR + MAP_REGION_SIZE,
|
2015-05-12 18:38:29 -07:00
|
|
|
};
|
|
|
|
|
2017-07-21 19:17:57 -07:00
|
|
|
/// Currently active page table
|
2017-09-24 14:42:42 -07:00
|
|
|
void SetCurrentPageTable(PageTable* page_table);
|
|
|
|
PageTable* GetCurrentPageTable();
|
2017-07-21 19:17:57 -07:00
|
|
|
|
2017-09-26 15:27:44 -07:00
|
|
|
/// Determines if the given VAddr is valid for the specified process.
|
|
|
|
bool IsValidVirtualAddress(const Kernel::Process& process, const VAddr vaddr);
|
2016-04-16 00:46:11 -07:00
|
|
|
bool IsValidVirtualAddress(const VAddr addr);
|
2017-09-26 15:27:44 -07:00
|
|
|
|
2016-04-16 00:46:11 -07:00
|
|
|
bool IsValidPhysicalAddress(const PAddr addr);
|
|
|
|
|
2015-05-12 18:38:29 -07:00
|
|
|
u8 Read8(VAddr addr);
|
|
|
|
u16 Read16(VAddr addr);
|
|
|
|
u32 Read32(VAddr addr);
|
|
|
|
u64 Read64(VAddr addr);
|
|
|
|
|
|
|
|
void Write8(VAddr addr, u8 data);
|
|
|
|
void Write16(VAddr addr, u16 data);
|
|
|
|
void Write32(VAddr addr, u32 data);
|
|
|
|
void Write64(VAddr addr, u64 data);
|
|
|
|
|
2017-09-29 17:38:54 -07:00
|
|
|
void ReadBlock(const Kernel::Process& process, const VAddr src_addr, void* dest_buffer,
|
|
|
|
size_t size);
|
2016-04-19 12:08:02 -07:00
|
|
|
void ReadBlock(const VAddr src_addr, void* dest_buffer, size_t size);
|
2017-09-29 20:42:25 -07:00
|
|
|
void WriteBlock(const Kernel::Process& process, const VAddr dest_addr, const void* src_buffer,
|
|
|
|
size_t size);
|
2016-04-19 12:08:02 -07:00
|
|
|
void WriteBlock(const VAddr dest_addr, const void* src_buffer, size_t size);
|
2016-04-16 02:21:41 -07:00
|
|
|
void ZeroBlock(const VAddr dest_addr, const size_t size);
|
2016-04-16 07:22:45 -07:00
|
|
|
void CopyBlock(VAddr dest_addr, VAddr src_addr, size_t size);
|
2015-05-12 18:38:29 -07:00
|
|
|
|
|
|
|
u8* GetPointer(VAddr virtual_address);
|
|
|
|
|
2016-06-27 10:42:42 -07:00
|
|
|
std::string ReadCString(VAddr virtual_address, std::size_t max_length);
|
|
|
|
|
2015-07-29 07:54:44 -07:00
|
|
|
/**
|
2017-06-21 20:25:46 -07:00
|
|
|
* Converts a virtual address inside a region with 1:1 mapping to physical memory to a physical
|
|
|
|
* address. This should be used by services to translate addresses for use by the hardware.
|
|
|
|
*/
|
|
|
|
boost::optional<PAddr> TryVirtualToPhysicalAddress(VAddr addr);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Converts a virtual address inside a region with 1:1 mapping to physical memory to a physical
|
|
|
|
* address. This should be used by services to translate addresses for use by the hardware.
|
|
|
|
*
|
|
|
|
* @deprecated Use TryVirtualToPhysicalAddress(), which reports failure.
|
|
|
|
*/
|
2015-07-29 07:54:44 -07:00
|
|
|
PAddr VirtualToPhysicalAddress(VAddr addr);
|
|
|
|
|
|
|
|
/**
|
2017-06-21 20:21:49 -07:00
|
|
|
* Undoes a mapping performed by VirtualToPhysicalAddress().
|
|
|
|
*/
|
|
|
|
boost::optional<VAddr> PhysicalToVirtualAddress(PAddr addr);
|
2015-07-29 07:54:44 -07:00
|
|
|
|
2015-05-12 18:38:29 -07:00
|
|
|
/**
|
|
|
|
* Gets a pointer to the memory region beginning at the specified physical address.
|
|
|
|
*/
|
|
|
|
u8* GetPhysicalPointer(PAddr address);
|
|
|
|
|
2018-03-22 19:56:41 -07:00
|
|
|
enum class FlushMode {
|
|
|
|
/// Write back modified surfaces to RAM
|
|
|
|
Flush,
|
|
|
|
/// Remove region from the cache
|
|
|
|
Invalidate,
|
|
|
|
/// Write back modified surfaces to RAM, and also remove them from the cache
|
|
|
|
FlushAndInvalidate,
|
|
|
|
};
|
|
|
|
|
2018-03-24 19:21:14 -07:00
|
|
|
/**
|
|
|
|
* Mark each page touching the region as cached.
|
|
|
|
*/
|
2018-04-23 21:19:36 -07:00
|
|
|
void RasterizerMarkRegionCached(Tegra::GPUVAddr start, u64 size, bool cached);
|
2018-03-24 19:21:14 -07:00
|
|
|
|
2018-03-22 19:56:41 -07:00
|
|
|
/**
|
|
|
|
* Flushes and invalidates any externally cached rasterizer resources touching the given virtual
|
|
|
|
* address region.
|
|
|
|
*/
|
2018-03-23 12:01:45 -07:00
|
|
|
void RasterizerFlushVirtualRegion(VAddr start, u64 size, FlushMode mode);
|
2018-03-22 19:56:41 -07:00
|
|
|
|
2017-07-21 19:17:57 -07:00
|
|
|
} // namespace Memory
|