2018-03-18 13:15:05 -07:00
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// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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2018-08-10 15:39:37 -07:00
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#include "common/assert.h"
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2018-03-18 13:15:05 -07:00
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#include "video_core/engines/fermi_2d.h"
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2018-09-08 13:58:20 -07:00
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#include "video_core/engines/kepler_memory.h"
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2018-03-18 13:15:05 -07:00
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/maxwell_compute.h"
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2018-06-10 15:02:33 -07:00
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#include "video_core/engines/maxwell_dma.h"
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2018-03-18 13:15:05 -07:00
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#include "video_core/gpu.h"
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2018-08-03 09:55:58 -07:00
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#include "video_core/rasterizer_interface.h"
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2018-03-18 13:15:05 -07:00
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namespace Tegra {
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2018-08-10 15:39:37 -07:00
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u32 FramebufferConfig::BytesPerPixel(PixelFormat format) {
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switch (format) {
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case PixelFormat::ABGR8:
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return 4;
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2018-11-20 17:27:34 -08:00
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default:
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return 4;
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2018-08-10 15:39:37 -07:00
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}
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UNREACHABLE();
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}
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2018-08-03 09:55:58 -07:00
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GPU::GPU(VideoCore::RasterizerInterface& rasterizer) {
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2018-08-28 07:57:56 -07:00
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memory_manager = std::make_unique<Tegra::MemoryManager>();
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2018-11-23 20:20:56 -08:00
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dma_pusher = std::make_unique<Tegra::DmaPusher>(*this);
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2018-08-03 09:55:58 -07:00
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maxwell_3d = std::make_unique<Engines::Maxwell3D>(rasterizer, *memory_manager);
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2018-10-05 20:46:40 -07:00
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fermi_2d = std::make_unique<Engines::Fermi2D>(rasterizer, *memory_manager);
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maxwell_compute = std::make_unique<Engines::MaxwellCompute>();
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2018-10-17 18:29:10 -07:00
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maxwell_dma = std::make_unique<Engines::MaxwellDMA>(rasterizer, *memory_manager);
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2018-10-17 17:44:07 -07:00
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kepler_memory = std::make_unique<Engines::KeplerMemory>(rasterizer, *memory_manager);
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2018-03-18 13:15:05 -07:00
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}
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GPU::~GPU() = default;
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2018-08-28 07:57:56 -07:00
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Engines::Maxwell3D& GPU::Maxwell3D() {
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2018-07-20 15:31:36 -07:00
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return *maxwell_3d;
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}
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2018-08-28 07:57:56 -07:00
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const Engines::Maxwell3D& GPU::Maxwell3D() const {
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2018-03-22 13:19:35 -07:00
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return *maxwell_3d;
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}
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2018-08-28 07:57:56 -07:00
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MemoryManager& GPU::MemoryManager() {
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return *memory_manager;
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}
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const MemoryManager& GPU::MemoryManager() const {
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return *memory_manager;
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}
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2018-11-23 20:20:56 -08:00
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DmaPusher& GPU::DmaPusher() {
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return *dma_pusher;
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}
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const DmaPusher& GPU::DmaPusher() const {
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return *dma_pusher;
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}
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2018-04-24 19:57:10 -07:00
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u32 RenderTargetBytesPerPixel(RenderTargetFormat format) {
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ASSERT(format != RenderTargetFormat::NONE);
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switch (format) {
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case RenderTargetFormat::RGBA32_FLOAT:
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case RenderTargetFormat::RGBA32_UINT:
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return 16;
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2018-08-12 21:04:52 -07:00
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case RenderTargetFormat::RGBA16_UINT:
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case RenderTargetFormat::RGBA16_UNORM:
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case RenderTargetFormat::RGBA16_FLOAT:
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case RenderTargetFormat::RG32_FLOAT:
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case RenderTargetFormat::RG32_UINT:
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return 8;
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case RenderTargetFormat::RGBA8_UNORM:
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case RenderTargetFormat::RGBA8_SNORM:
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case RenderTargetFormat::RGBA8_SRGB:
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2018-08-20 05:26:54 -07:00
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case RenderTargetFormat::RGBA8_UINT:
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case RenderTargetFormat::RGB10_A2_UNORM:
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case RenderTargetFormat::BGRA8_UNORM:
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case RenderTargetFormat::BGRA8_SRGB:
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case RenderTargetFormat::RG16_UNORM:
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case RenderTargetFormat::RG16_SNORM:
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case RenderTargetFormat::RG16_UINT:
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case RenderTargetFormat::RG16_SINT:
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case RenderTargetFormat::RG16_FLOAT:
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2018-08-01 06:31:42 -07:00
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case RenderTargetFormat::R32_FLOAT:
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2018-08-07 23:40:04 -07:00
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case RenderTargetFormat::R11G11B10_FLOAT:
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case RenderTargetFormat::R32_UINT:
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return 4;
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case RenderTargetFormat::R16_UNORM:
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case RenderTargetFormat::R16_SNORM:
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case RenderTargetFormat::R16_UINT:
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case RenderTargetFormat::R16_SINT:
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case RenderTargetFormat::R16_FLOAT:
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2018-08-12 20:02:34 -07:00
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case RenderTargetFormat::RG8_UNORM:
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2018-08-10 09:07:37 -07:00
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case RenderTargetFormat::RG8_SNORM:
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2018-08-11 11:01:50 -07:00
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return 2;
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case RenderTargetFormat::R8_UNORM:
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case RenderTargetFormat::R8_UINT:
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return 1;
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2018-04-24 19:57:10 -07:00
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default:
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2018-04-27 04:54:05 -07:00
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UNIMPLEMENTED_MSG("Unimplemented render target format {}", static_cast<u32>(format));
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2018-04-24 19:57:10 -07:00
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}
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}
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2018-08-11 11:01:50 -07:00
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u32 DepthFormatBytesPerPixel(DepthFormat format) {
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switch (format) {
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case DepthFormat::Z32_S8_X24_FLOAT:
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return 8;
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case DepthFormat::Z32_FLOAT:
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case DepthFormat::S8_Z24_UNORM:
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case DepthFormat::Z24_X8_UNORM:
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case DepthFormat::Z24_S8_UNORM:
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case DepthFormat::Z24_C8_UNORM:
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return 4;
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case DepthFormat::Z16_UNORM:
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return 2;
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default:
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UNIMPLEMENTED_MSG("Unimplemented Depth format {}", static_cast<u32>(format));
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}
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}
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2018-11-23 20:20:56 -08:00
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enum class BufferMethods {
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BindObject = 0,
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CountBufferMethods = 0x40,
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};
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void GPU::CallMethod(const MethodCall& method_call) {
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2018-11-30 23:05:19 -08:00
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LOG_TRACE(HW_GPU, "Processing method {:08X} on subchannel {}", method_call.method,
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method_call.subchannel);
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2018-11-23 20:20:56 -08:00
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ASSERT(method_call.subchannel < bound_engines.size());
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if (method_call.method == static_cast<u32>(BufferMethods::BindObject)) {
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// Bind the current subchannel to the desired engine id.
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LOG_DEBUG(HW_GPU, "Binding subchannel {} to engine {}", method_call.subchannel,
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method_call.argument);
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bound_engines[method_call.subchannel] = static_cast<EngineID>(method_call.argument);
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return;
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}
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const EngineID engine = bound_engines[method_call.subchannel];
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switch (engine) {
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case EngineID::FERMI_TWOD_A:
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fermi_2d->CallMethod(method_call);
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break;
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case EngineID::MAXWELL_B:
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maxwell_3d->CallMethod(method_call);
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break;
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case EngineID::MAXWELL_COMPUTE_B:
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maxwell_compute->CallMethod(method_call);
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break;
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case EngineID::MAXWELL_DMA_COPY_A:
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maxwell_dma->CallMethod(method_call);
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break;
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case EngineID::KEPLER_INLINE_TO_MEMORY_B:
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kepler_memory->CallMethod(method_call);
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break;
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default:
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UNIMPLEMENTED_MSG("Unimplemented engine");
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}
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}
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2018-03-18 13:15:05 -07:00
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} // namespace Tegra
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