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Merge pull request #869 from Subv/ubsan

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Corrected a few error cases detected by asan/ubsan
This commit is contained in:
bunnei 2018-07-31 09:24:13 -07:00 committed by GitHub
commit 3575c076cb
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4 changed files with 23 additions and 8 deletions
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14
src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.cpp
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@ -97,7 +97,9 @@ u32 nvhost_ctrl_gpu::GetTPCMasks(const std::vector<u8>& input, std::vector<u8>&
u32 nvhost_ctrl_gpu::GetActiveSlotMask(const std::vector<u8>& input, std::vector<u8>& output) { u32 nvhost_ctrl_gpu::GetActiveSlotMask(const std::vector<u8>& input, std::vector<u8>& output) {
LOG_DEBUG(Service_NVDRV, "called"); LOG_DEBUG(Service_NVDRV, "called");
IoctlActiveSlotMask params{}; IoctlActiveSlotMask params{};
std::memcpy(&params, input.data(), input.size()); if (input.size() > 0) {
std::memcpy(&params, input.data(), input.size());
}
params.slot = 0x07; params.slot = 0x07;
params.mask = 0x01; params.mask = 0x01;
std::memcpy(output.data(), &params, output.size()); std::memcpy(output.data(), &params, output.size());
@ -107,7 +109,9 @@ u32 nvhost_ctrl_gpu::GetActiveSlotMask(const std::vector<u8>& input, std::vector
u32 nvhost_ctrl_gpu::ZCullGetCtxSize(const std::vector<u8>& input, std::vector<u8>& output) { u32 nvhost_ctrl_gpu::ZCullGetCtxSize(const std::vector<u8>& input, std::vector<u8>& output) {
LOG_DEBUG(Service_NVDRV, "called"); LOG_DEBUG(Service_NVDRV, "called");
IoctlZcullGetCtxSize params{}; IoctlZcullGetCtxSize params{};
std::memcpy(&params, input.data(), input.size()); if (input.size() > 0) {
std::memcpy(&params, input.data(), input.size());
}
params.size = 0x1; params.size = 0x1;
std::memcpy(output.data(), &params, output.size()); std::memcpy(output.data(), &params, output.size());
return 0; return 0;
@ -116,7 +120,11 @@ u32 nvhost_ctrl_gpu::ZCullGetCtxSize(const std::vector<u8>& input, std::vector<u
u32 nvhost_ctrl_gpu::ZCullGetInfo(const std::vector<u8>& input, std::vector<u8>& output) { u32 nvhost_ctrl_gpu::ZCullGetInfo(const std::vector<u8>& input, std::vector<u8>& output) {
LOG_DEBUG(Service_NVDRV, "called"); LOG_DEBUG(Service_NVDRV, "called");
IoctlNvgpuGpuZcullGetInfoArgs params{}; IoctlNvgpuGpuZcullGetInfoArgs params{};
std::memcpy(&params, input.data(), input.size());
if (input.size() > 0) {
std::memcpy(&params, input.data(), input.size());
}
params.width_align_pixels = 0x20; params.width_align_pixels = 0x20;
params.height_align_pixels = 0x20; params.height_align_pixels = 0x20;
params.pixel_squares_by_aliquots = 0x400; params.pixel_squares_by_aliquots = 0x400;

9
src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp
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@ -132,9 +132,12 @@ u32 nvhost_gpu::SubmitGPFIFO(const std::vector<u8>& input, std::vector<u8>& outp
LOG_WARNING(Service_NVDRV, "(STUBBED) called, gpfifo={:X}, num_entries={:X}, flags={:X}", LOG_WARNING(Service_NVDRV, "(STUBBED) called, gpfifo={:X}, num_entries={:X}, flags={:X}",
params.address, params.num_entries, params.flags); params.address, params.num_entries, params.flags);
auto entries = std::vector<IoctlGpfifoEntry>(); ASSERT_MSG(input.size() ==
entries.resize(params.num_entries); sizeof(IoctlSubmitGpfifo) + params.num_entries * sizeof(IoctlGpfifoEntry),
std::memcpy(&entries[0], &input.data()[sizeof(IoctlSubmitGpfifo)], "Incorrect input size");
std::vector<IoctlGpfifoEntry> entries(params.num_entries);
std::memcpy(entries.data(), &input[sizeof(IoctlSubmitGpfifo)],
params.num_entries * sizeof(IoctlGpfifoEntry)); params.num_entries * sizeof(IoctlGpfifoEntry));
for (auto entry : entries) { for (auto entry : entries) {
Tegra::GPUVAddr va_addr = entry.Address(); Tegra::GPUVAddr va_addr = entry.Address();

4
src/video_core/macro_interpreter.cpp
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@ -102,11 +102,11 @@ bool MacroInterpreter::Step(const std::vector<u32>& code, bool is_delay_slot) {
if (taken) { if (taken) {
// Ignore the delay slot if the branch has the annul bit. // Ignore the delay slot if the branch has the annul bit.
if (opcode.branch_annul) { if (opcode.branch_annul) {
pc = base_address + (opcode.immediate << 2); pc = base_address + opcode.GetBranchTarget();
return true; return true;
} }
delayed_pc = base_address + (opcode.immediate << 2); delayed_pc = base_address + opcode.GetBranchTarget();
// Execute one more instruction due to the delay slot. // Execute one more instruction due to the delay slot.
return Step(code, true); return Step(code, true);
} }

4
src/video_core/macro_interpreter.h
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@ -91,6 +91,10 @@ private:
u32 GetBitfieldMask() const { u32 GetBitfieldMask() const {
return (1 << bf_size) - 1; return (1 << bf_size) - 1;
} }
s32 GetBranchTarget() const {
return static_cast<s32>(immediate * sizeof(u32));
}
}; };
union MethodAddress { union MethodAddress {