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shader/decode: Reduce severity of arithmetic rounding warnings

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This commit is contained in:
ReinUsesLisp 2019-11-04 02:24:58 -03:00
parent c4374d0d41
commit 39c66abd91
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GPG Key ID: 2DFC508897B39CFE
6 changed files with 17 additions and 15 deletions
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4
src/video_core/shader/decode/arithmetic.cpp
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@ -43,11 +43,11 @@ u32 ShaderIR::DecodeArithmetic(NodeBlock& bb, u32 pc) {
case OpCode::Id::FMUL_IMM: { case OpCode::Id::FMUL_IMM: {
// FMUL does not have 'abs' bits and only the second operand has a 'neg' bit. // FMUL does not have 'abs' bits and only the second operand has a 'neg' bit.
if (instr.fmul.tab5cb8_2 != 0) { if (instr.fmul.tab5cb8_2 != 0) {
LOG_WARNING(HW_GPU, "FMUL tab5cb8_2({}) is not implemented", LOG_DEBUG(HW_GPU, "FMUL tab5cb8_2({}) is not implemented",
instr.fmul.tab5cb8_2.Value()); instr.fmul.tab5cb8_2.Value());
} }
if (instr.fmul.tab5c68_0 != 1) { if (instr.fmul.tab5c68_0 != 1) {
LOG_WARNING(HW_GPU, "FMUL tab5cb8_0({}) is not implemented", LOG_DEBUG(HW_GPU, "FMUL tab5cb8_0({}) is not implemented",
instr.fmul.tab5c68_0.Value()); instr.fmul.tab5c68_0.Value());
} }

4
src/video_core/shader/decode/arithmetic_half.cpp
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@ -21,8 +21,8 @@ u32 ShaderIR::DecodeArithmeticHalf(NodeBlock& bb, u32 pc) {
if (opcode->get().GetId() == OpCode::Id::HADD2_C || if (opcode->get().GetId() == OpCode::Id::HADD2_C ||
opcode->get().GetId() == OpCode::Id::HADD2_R) { opcode->get().GetId() == OpCode::Id::HADD2_R) {
if (instr.alu_half.ftz != 0) { if (instr.alu_half.ftz == 0) {
LOG_WARNING(HW_GPU, "{} FTZ not implemented", opcode->get().GetName()); LOG_DEBUG(HW_GPU, "{} without FTZ is not implemented", opcode->get().GetName());
} }
} }

8
src/video_core/shader/decode/arithmetic_half_immediate.cpp
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@ -19,12 +19,12 @@ u32 ShaderIR::DecodeArithmeticHalfImmediate(NodeBlock& bb, u32 pc) {
const auto opcode = OpCode::Decode(instr); const auto opcode = OpCode::Decode(instr);
if (opcode->get().GetId() == OpCode::Id::HADD2_IMM) { if (opcode->get().GetId() == OpCode::Id::HADD2_IMM) {
if (instr.alu_half_imm.ftz != 0) { if (instr.alu_half_imm.ftz == 0) {
LOG_WARNING(HW_GPU, "{} FTZ not implemented", opcode->get().GetName()); LOG_DEBUG(HW_GPU, "{} without FTZ is not implemented", opcode->get().GetName());
} }
} else { } else {
if (instr.alu_half_imm.precision != Tegra::Shader::HalfPrecision::None) { if (instr.alu_half_imm.precision != Tegra::Shader::HalfPrecision::FTZ) {
LOG_WARNING(HW_GPU, "{} FTZ not implemented", opcode->get().GetName()); LOG_DEBUG(HW_GPU, "{} without FTZ is not implemented", opcode->get().GetName());
} }
} }

4
src/video_core/shader/decode/ffma.cpp
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@ -19,10 +19,10 @@ u32 ShaderIR::DecodeFfma(NodeBlock& bb, u32 pc) {
UNIMPLEMENTED_IF_MSG(instr.ffma.cc != 0, "FFMA cc not implemented"); UNIMPLEMENTED_IF_MSG(instr.ffma.cc != 0, "FFMA cc not implemented");
if (instr.ffma.tab5980_0 != 1) { if (instr.ffma.tab5980_0 != 1) {
LOG_WARNING(HW_GPU, "FFMA tab5980_0({}) not implemented", instr.ffma.tab5980_0.Value()); LOG_DEBUG(HW_GPU, "FFMA tab5980_0({}) not implemented", instr.ffma.tab5980_0.Value());
} }
if (instr.ffma.tab5980_1 != 0) { if (instr.ffma.tab5980_1 != 0) {
LOG_WARNING(HW_GPU, "FFMA tab5980_1({}) not implemented", instr.ffma.tab5980_1.Value()); LOG_DEBUG(HW_GPU, "FFMA tab5980_1({}) not implemented", instr.ffma.tab5980_1.Value());
} }
const Node op_a = GetRegister(instr.gpr8); const Node op_a = GetRegister(instr.gpr8);

4
src/video_core/shader/decode/half_set.cpp
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@ -20,8 +20,8 @@ u32 ShaderIR::DecodeHalfSet(NodeBlock& bb, u32 pc) {
const Instruction instr = {program_code[pc]}; const Instruction instr = {program_code[pc]};
const auto opcode = OpCode::Decode(instr); const auto opcode = OpCode::Decode(instr);
if (instr.hset2.ftz != 0) { if (instr.hset2.ftz == 0) {
LOG_WARNING(HW_GPU, "{} FTZ not implemented", opcode->get().GetName()); LOG_DEBUG(HW_GPU, "{} without FTZ is not implemented", opcode->get().GetName());
} }
Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.hset2.type_a); Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.hset2.type_a);

4
src/video_core/shader/decode/half_set_predicate.cpp
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@ -19,7 +19,9 @@ u32 ShaderIR::DecodeHalfSetPredicate(NodeBlock& bb, u32 pc) {
const Instruction instr = {program_code[pc]}; const Instruction instr = {program_code[pc]};
const auto opcode = OpCode::Decode(instr); const auto opcode = OpCode::Decode(instr);
LOG_DEBUG(HW_GPU, "ftz={}", static_cast<u32>(instr.hsetp2.ftz)); if (instr.hsetp2.ftz != 0) {
LOG_DEBUG(HW_GPU, "{} without FTZ is not implemented", opcode->get().GetName());
}
Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.hsetp2.type_a); Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.hsetp2.type_a);
op_a = GetOperandAbsNegHalf(op_a, instr.hsetp2.abs_a, instr.hsetp2.negate_a); op_a = GetOperandAbsNegHalf(op_a, instr.hsetp2.abs_a, instr.hsetp2.negate_a);