Commit Graph

16 Commits

Author SHA1 Message Date
05d41fa9b7 shader: Add support for "negative" and unaligned offsets
"Negative" offsets don't exist. They are shown as such due to a bug in
nvdisasm.

Unaligned offsets have been proved to read the aligned offset. For
example, when reading an U32, if the offset is 6, the offset read will
be 4.
2021-07-22 21:51:34 -04:00
0bb85f6a75 shader_recompiler,video_core: Cleanup some GCC and Clang errors
Mostly fixing unused *, implicit conversion, braced scalar init,
fpermissive, and some others.

Some Clang errors likely remain in video_core, and std::ranges is still
a pertinent issue in shader_recompiler

shader_recompiler: cmake: Force bracket depth to 1024 on Clang
Increases the maximum fold expression depth

thread_worker: Include condition_variable

Don't use list initializers in control flow

Co-authored-by: ReinUsesLisp <reinuseslisp@airmail.cc>
2021-07-22 21:51:26 -04:00
6c51f49632 shader: Implement FSWZADD 2021-07-22 21:51:25 -04:00
8cb9443cb9 shader: Fix F2I 2021-07-22 21:51:24 -04:00
c858b8ba97 shader: Implement DMUL and DFMA
Also add a missing const on DADD
2021-07-22 21:51:24 -04:00
112b8f00f0 shader: Add FP64 register load/store helpers 2021-07-22 21:51:24 -04:00
f91859efd2 shader: Implement I2F 2021-07-22 21:51:23 -04:00
72990df7ba shader: Implement DADD 2021-07-22 21:51:23 -04:00
3a63fa0477 shader: Partial implementation of LDC 2021-07-22 21:51:23 -04:00
e44752ddc8 shader: FMUL, select, RRO, and MUFU fixes 2021-07-22 21:51:22 -04:00
274897dfd5 spirv: Fixes and Intel specific workarounds 2021-07-22 21:51:22 -04:00
704c6f353f shader: Rename, implement FADD.SAT and P2R (imm) 2021-07-22 21:51:22 -04:00
85cce78583 shader: Primitive Vulkan integration 2021-07-22 21:51:22 -04:00
be94ee88d2 shader: Make typed IR 2021-07-22 21:51:21 -04:00
d24a16045f shader: Initial instruction support 2021-07-22 21:51:21 -04:00
2d48a7b4d0 shader: Initial recompiler work 2021-07-22 21:51:21 -04:00