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https://github.com/yuzu-emu/yuzu-android
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99ceb03a1c
This formats all copyright comments according to SPDX formatting guidelines. Additionally, this resolves the remaining GPLv2 only licensed files by relicensing them to GPLv2.0-or-later.
116 lines
3.4 KiB
C++
116 lines
3.4 KiB
C++
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/common_funcs.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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enum class LogicalOp : u64 {
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AND,
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OR,
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XOR,
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PASS_B,
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};
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[[nodiscard]] IR::U32 LogicalOperation(IR::IREmitter& ir, const IR::U32& operand_1,
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const IR::U32& operand_2, LogicalOp op) {
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switch (op) {
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case LogicalOp::AND:
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return ir.BitwiseAnd(operand_1, operand_2);
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case LogicalOp::OR:
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return ir.BitwiseOr(operand_1, operand_2);
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case LogicalOp::XOR:
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return ir.BitwiseXor(operand_1, operand_2);
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case LogicalOp::PASS_B:
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return operand_2;
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default:
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throw NotImplementedException("Invalid Logical operation {}", op);
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}
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}
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void LOP(TranslatorVisitor& v, u64 insn, IR::U32 op_b, bool x, bool cc, bool inv_a, bool inv_b,
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LogicalOp bit_op, std::optional<PredicateOp> pred_op = std::nullopt,
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IR::Pred dest_pred = IR::Pred::PT) {
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union {
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u64 insn;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> src_reg;
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} const lop{insn};
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if (x) {
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throw NotImplementedException("X");
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}
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IR::U32 op_a{v.X(lop.src_reg)};
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if (inv_a != 0) {
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op_a = v.ir.BitwiseNot(op_a);
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}
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if (inv_b != 0) {
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op_b = v.ir.BitwiseNot(op_b);
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}
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const IR::U32 result{LogicalOperation(v.ir, op_a, op_b, bit_op)};
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if (pred_op) {
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const IR::U1 pred_result{PredicateOperation(v.ir, result, *pred_op)};
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v.ir.SetPred(dest_pred, pred_result);
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}
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if (cc) {
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if (bit_op == LogicalOp::PASS_B) {
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v.SetZFlag(v.ir.IEqual(result, v.ir.Imm32(0)));
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v.SetSFlag(v.ir.ILessThan(result, v.ir.Imm32(0), true));
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} else {
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v.SetZFlag(v.ir.GetZeroFromOp(result));
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v.SetSFlag(v.ir.GetSignFromOp(result));
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}
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v.ResetCFlag();
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v.ResetOFlag();
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}
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v.X(lop.dest_reg, result);
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}
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void LOP(TranslatorVisitor& v, u64 insn, const IR::U32& op_b) {
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union {
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u64 insn;
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BitField<39, 1, u64> inv_a;
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BitField<40, 1, u64> inv_b;
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BitField<41, 2, LogicalOp> bit_op;
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BitField<43, 1, u64> x;
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BitField<44, 2, PredicateOp> pred_op;
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BitField<47, 1, u64> cc;
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BitField<48, 3, IR::Pred> dest_pred;
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} const lop{insn};
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LOP(v, insn, op_b, lop.x != 0, lop.cc != 0, lop.inv_a != 0, lop.inv_b != 0, lop.bit_op,
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lop.pred_op, lop.dest_pred);
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}
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} // Anonymous namespace
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void TranslatorVisitor::LOP_reg(u64 insn) {
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LOP(*this, insn, GetReg20(insn));
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}
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void TranslatorVisitor::LOP_cbuf(u64 insn) {
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LOP(*this, insn, GetCbuf(insn));
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}
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void TranslatorVisitor::LOP_imm(u64 insn) {
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LOP(*this, insn, GetImm20(insn));
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}
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void TranslatorVisitor::LOP32I(u64 insn) {
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union {
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u64 raw;
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BitField<53, 2, LogicalOp> bit_op;
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BitField<57, 1, u64> x;
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BitField<52, 1, u64> cc;
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BitField<55, 1, u64> inv_a;
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BitField<56, 1, u64> inv_b;
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} const lop32i{insn};
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LOP(*this, insn, GetImm32(insn), lop32i.x != 0, lop32i.cc != 0, lop32i.inv_a != 0,
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lop32i.inv_b != 0, lop32i.bit_op);
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}
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} // namespace Shader::Maxwell
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