mirror of
https://github.com/yuzu-emu/yuzu-android
synced 2025-01-09 19:42:26 -08:00
0bb85f6a75
Mostly fixing unused *, implicit conversion, braced scalar init, fpermissive, and some others. Some Clang errors likely remain in video_core, and std::ranges is still a pertinent issue in shader_recompiler shader_recompiler: cmake: Force bracket depth to 1024 on Clang Increases the maximum fold expression depth thread_worker: Include condition_variable Don't use list initializers in control flow Co-authored-by: ReinUsesLisp <reinuseslisp@airmail.cc>
77 lines
2.0 KiB
C++
77 lines
2.0 KiB
C++
// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <optional>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/ir/modifiers.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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enum class Mode : u64 {
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Dimension = 1,
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TextureType = 2,
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SamplePos = 5,
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};
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IR::Value Query(TranslatorVisitor& v, const IR::U32& handle, Mode mode, IR::Reg src_reg) {
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switch (mode) {
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case Mode::Dimension: {
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const IR::U32 lod{v.X(src_reg)};
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return v.ir.ImageQueryDimension(handle, lod);
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}
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case Mode::TextureType:
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case Mode::SamplePos:
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default:
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throw NotImplementedException("Mode {}", mode);
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}
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}
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void Impl(TranslatorVisitor& v, u64 insn, std::optional<u32> cbuf_offset) {
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union {
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u64 raw;
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BitField<49, 1, u64> nodep;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> src_reg;
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BitField<22, 3, Mode> mode;
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BitField<31, 4, u64> mask;
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} const txq{insn};
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IR::Reg src_reg{txq.src_reg};
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IR::U32 handle;
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if (cbuf_offset) {
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handle = v.ir.Imm32(*cbuf_offset);
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} else {
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handle = v.X(src_reg);
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++src_reg;
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}
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const IR::Value query{Query(v, handle, txq.mode, src_reg)};
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IR::Reg dest_reg{txq.dest_reg};
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for (int element = 0; element < 4; ++element) {
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if (((txq.mask >> element) & 1) == 0) {
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continue;
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}
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v.X(dest_reg, IR::U32{v.ir.CompositeExtract(query, static_cast<size_t>(element))});
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++dest_reg;
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}
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}
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} // Anonymous namespace
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void TranslatorVisitor::TXQ(u64 insn) {
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union {
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u64 raw;
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BitField<36, 13, u64> cbuf_offset;
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} const txq{insn};
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Impl(*this, insn, static_cast<u32>(txq.cbuf_offset * 4));
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}
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void TranslatorVisitor::TXQ_b(u64 insn) {
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Impl(*this, insn, std::nullopt);
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}
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} // namespace Shader::Maxwell
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