daniel/Ryujinx
1
0
Fork 0
mirror of https://github.com/Ryujinx/Ryujinx.git synced 2024-12-23 11:01:20 -08:00
Code Issues Packages Projects Releases Wiki Activity

Implement CSDB instruction (#2927)

Browse Source
This commit is contained in:
gdkchan 2021-12-19 11:19:05 -03:00 committed by GitHub
parent 267b248c13
commit e24949ca2c
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 12 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
ARMeilleure/Decoders/OpCodeTable.cs
View File

@ -661,6 +661,7 @@ namespace ARMeilleure.Decoders
SetA32("<<<<00010100xxxxxxxx00100100xxxx", InstName.Crc32cw, InstEmit32.Crc32cw, OpCode32AluReg.Create);
SetA32("<<<<00010010xxxxxxxx00000100xxxx", InstName.Crc32h, InstEmit32.Crc32h, OpCode32AluReg.Create);
SetA32("<<<<00010100xxxxxxxx00000100xxxx", InstName.Crc32w, InstEmit32.Crc32w, OpCode32AluReg.Create);
SetA32("<<<<0011001000001111000000010100", InstName.Csdb, InstEmit32.Csdb, OpCode32.Create);
SetA32("1111010101111111111100000101xxxx", InstName.Dmb, InstEmit32.Dmb, OpCode32.Create);
SetA32("1111010101111111111100000100xxxx", InstName.Dsb, InstEmit32.Dsb, OpCode32.Create);
SetA32("<<<<0010001xxxxxxxxxxxxxxxxxxxxx", InstName.Eor, InstEmit32.Eor, OpCode32AluImm.Create);

5
ARMeilleure/Instructions/InstEmitMemoryEx32.cs
View File

@ -16,6 +16,11 @@ namespace ARMeilleure.Instructions
EmitClearExclusive(context);
}
public static void Csdb(ArmEmitterContext context)
{
// Execute as no-op.
}
public static void Dmb(ArmEmitterContext context) => EmitBarrier(context);
public static void Dsb(ArmEmitterContext context) => EmitBarrier(context);

10
ARMeilleure/Instructions/InstEmitSimdMemory32.cs
View File

@ -99,7 +99,7 @@ namespace ARMeilleure.Instructions
EmitLoadSimd(context, address, GetVecA32(dreg >> 1), dreg >> 1, rIndex++, op.Size);
}
}
}
}
else
{
EmitLoadSimd(context, address, GetVecA32(d >> 1), d >> 1, index, op.Size);
@ -120,13 +120,13 @@ namespace ARMeilleure.Instructions
{
Operand m = GetIntA32(context, op.Rm);
SetIntA32(context, op.Rn, context.Add(n, m));
}
}
else
{
SetIntA32(context, op.Rn, context.Add(n, Const(count * eBytes)));
}
}
}
}
else
{
OpCode32SimdMemPair op = (OpCode32SimdMemPair)context.CurrOp;
@ -161,7 +161,7 @@ namespace ARMeilleure.Instructions
}
else
{
if (load)
{
EmitLoadSimd(context, address, GetVecA32(elemD >> 1), elemD >> 1, index, op.Size);
@ -213,7 +213,7 @@ namespace ARMeilleure.Instructions
int sReg = (op.DoubleWidth) ? (op.Vd << 1) : op.Vd;
int offset = 0;
int byteSize = 4;
for (int num = 0; num < range; num++, sReg++)
{
Operand address = context.Add(baseAddress, Const(offset));

1
ARMeilleure/Instructions/InstName.cs
View File

@ -36,6 +36,7 @@ namespace ARMeilleure.Instructions
Crc32ch,
Crc32cw,
Crc32cx,
Csdb,
Csel,
Csinc,
Csinv,