2014-04-08 16:15:46 -07:00
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// Copyright 2014 Citra Emulator Project
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2014-12-16 21:38:14 -08:00
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// Licensed under GPLv2 or any later version
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2014-04-08 16:15:46 -07:00
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// Refer to the license.txt file included.
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2013-09-18 20:52:51 -07:00
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2014-04-17 20:05:31 -07:00
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#include <map>
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2015-05-06 00:06:12 -07:00
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#include "common/common_types.h"
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#include "common/logging/log.h"
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#include "common/swap.h"
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2013-09-18 20:52:51 -07:00
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2014-04-08 17:15:08 -07:00
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#include "core/mem_map.h"
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#include "core/hw/hw.h"
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2014-05-06 20:32:04 -07:00
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#include "hle/config_mem.h"
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2015-01-01 21:41:34 -08:00
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#include "hle/shared_page.h"
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2013-09-18 20:52:51 -07:00
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namespace Memory {
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2014-11-18 05:48:11 -08:00
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static std::map<u32, MemoryBlock> heap_map;
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2014-11-22 19:35:45 -08:00
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static std::map<u32, MemoryBlock> heap_linear_map;
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2014-04-17 20:05:31 -07:00
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2015-05-08 23:08:11 -07:00
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PAddr VirtualToPhysicalAddress(const VAddr addr) {
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2015-02-08 05:38:00 -08:00
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if (addr == 0) {
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return 0;
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2015-05-08 23:08:11 -07:00
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} else if (addr >= VRAM_VADDR && addr < VRAM_VADDR_END) {
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return addr - VRAM_VADDR + VRAM_PADDR;
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} else if (addr >= LINEAR_HEAP_VADDR && addr < LINEAR_HEAP_VADDR_END) {
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return addr - LINEAR_HEAP_VADDR + FCRAM_PADDR;
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} else if (addr >= DSP_RAM_VADDR && addr < DSP_RAM_VADDR_END) {
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return addr - DSP_RAM_VADDR + DSP_RAM_PADDR;
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} else if (addr >= IO_AREA_VADDR && addr < IO_AREA_VADDR_END) {
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return addr - IO_AREA_VADDR + IO_AREA_PADDR;
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2014-08-02 16:46:47 -07:00
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}
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2015-05-08 23:08:11 -07:00
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LOG_ERROR(HW_Memory, "Unknown virtual address @ 0x%08x", addr);
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// To help with debugging, set bit on address so that it's obviously invalid.
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return addr | 0x80000000;
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2014-08-02 16:46:47 -07:00
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}
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2014-04-26 11:21:40 -07:00
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2015-05-08 23:08:11 -07:00
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VAddr PhysicalToVirtualAddress(const PAddr addr) {
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2015-02-08 05:38:00 -08:00
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if (addr == 0) {
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return 0;
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2015-05-08 23:08:11 -07:00
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} else if (addr >= VRAM_PADDR && addr < VRAM_PADDR_END) {
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return addr - VRAM_PADDR + VRAM_VADDR;
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} else if (addr >= FCRAM_PADDR && addr < FCRAM_PADDR_END) {
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return addr - FCRAM_PADDR + LINEAR_HEAP_VADDR;
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} else if (addr >= DSP_RAM_PADDR && addr < DSP_RAM_PADDR_END) {
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return addr - DSP_RAM_PADDR + DSP_RAM_VADDR;
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} else if (addr >= IO_AREA_PADDR && addr < IO_AREA_PADDR_END) {
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return addr - IO_AREA_PADDR + IO_AREA_VADDR;
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2014-04-17 15:40:42 -07:00
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}
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2014-08-02 16:46:47 -07:00
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2015-05-08 23:08:11 -07:00
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LOG_ERROR(HW_Memory, "Unknown physical address @ 0x%08x", addr);
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// To help with debugging, set bit on address so that it's obviously invalid.
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return addr | 0x80000000;
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2014-04-17 15:40:42 -07:00
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}
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2013-09-18 20:52:51 -07:00
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template <typename T>
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2014-08-28 11:20:55 -07:00
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inline void Read(T &var, const VAddr vaddr) {
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2014-04-01 15:18:02 -07:00
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// TODO: Figure out the fastest order of tests for both read and write (they are probably different).
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// TODO: Make sure this represents the mirrors in a correct way.
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// Could just do a base-relative read, too.... TODO
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2013-09-18 20:52:51 -07:00
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2014-05-07 18:04:55 -07:00
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// Kernel memory command buffer
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2015-05-08 20:39:56 -07:00
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if (vaddr >= TLS_AREA_VADDR && vaddr < TLS_AREA_VADDR_END) {
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var = *((const T*)&g_tls_mem[vaddr - TLS_AREA_VADDR]);
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2014-04-12 18:55:36 -07:00
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2014-04-29 20:16:12 -07:00
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// ExeFS:/.code is loaded here
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2015-05-08 20:39:56 -07:00
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} else if ((vaddr >= PROCESS_IMAGE_VADDR) && (vaddr < PROCESS_IMAGE_VADDR_END)) {
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var = *((const T*)&g_exefs_code[vaddr - PROCESS_IMAGE_VADDR]);
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2014-04-29 20:16:12 -07:00
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2014-11-22 19:35:45 -08:00
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// FCRAM - linear heap
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2015-05-08 20:39:56 -07:00
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} else if ((vaddr >= LINEAR_HEAP_VADDR) && (vaddr < LINEAR_HEAP_VADDR_END)) {
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var = *((const T*)&g_heap_linear[vaddr - LINEAR_HEAP_VADDR]);
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2014-04-17 18:15:40 -07:00
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2014-04-17 18:05:34 -07:00
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// FCRAM - application heap
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2014-04-24 20:56:06 -07:00
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} else if ((vaddr >= HEAP_VADDR) && (vaddr < HEAP_VADDR_END)) {
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2014-12-02 22:13:29 -08:00
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var = *((const T*)&g_heap[vaddr - HEAP_VADDR]);
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2014-04-17 15:40:42 -07:00
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2014-04-24 20:56:06 -07:00
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// Shared memory
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} else if ((vaddr >= SHARED_MEMORY_VADDR) && (vaddr < SHARED_MEMORY_VADDR_END)) {
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2014-12-02 22:13:29 -08:00
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var = *((const T*)&g_shared_mem[vaddr - SHARED_MEMORY_VADDR]);
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2014-04-24 20:56:06 -07:00
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2014-05-06 20:32:04 -07:00
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// Config memory
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} else if ((vaddr >= CONFIG_MEMORY_VADDR) && (vaddr < CONFIG_MEMORY_VADDR_END)) {
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ConfigMem::Read<T>(var, vaddr);
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2015-01-01 21:41:34 -08:00
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// Shared page
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} else if ((vaddr >= SHARED_PAGE_VADDR) && (vaddr < SHARED_PAGE_VADDR_END)) {
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SharedPage::Read<T>(var, vaddr);
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2014-12-29 19:35:06 -08:00
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// DSP memory
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2015-05-08 20:39:56 -07:00
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} else if ((vaddr >= DSP_RAM_VADDR) && (vaddr < DSP_RAM_VADDR_END)) {
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var = *((const T*)&g_dsp_mem[vaddr - DSP_RAM_VADDR]);
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2014-12-29 19:35:06 -08:00
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2014-04-25 22:27:25 -07:00
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// VRAM
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} else if ((vaddr >= VRAM_VADDR) && (vaddr < VRAM_VADDR_END)) {
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2014-12-02 22:13:29 -08:00
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var = *((const T*)&g_vram[vaddr - VRAM_VADDR]);
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2014-04-25 22:27:25 -07:00
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2014-04-03 19:04:50 -07:00
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} else {
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2014-12-05 17:53:49 -08:00
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LOG_ERROR(HW_Memory, "unknown Read%lu @ 0x%08X", sizeof(var) * 8, vaddr);
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2014-04-01 15:18:02 -07:00
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}
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2013-09-18 20:52:51 -07:00
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}
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template <typename T>
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2014-08-28 11:20:55 -07:00
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inline void Write(const VAddr vaddr, const T data) {
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2014-08-02 16:46:47 -07:00
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2014-05-07 18:04:55 -07:00
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// Kernel memory command buffer
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2015-05-08 20:39:56 -07:00
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if (vaddr >= TLS_AREA_VADDR && vaddr < TLS_AREA_VADDR_END) {
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*(T*)&g_tls_mem[vaddr - TLS_AREA_VADDR] = data;
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2014-04-12 18:55:36 -07:00
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2014-04-29 20:16:12 -07:00
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// ExeFS:/.code is loaded here
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2015-05-08 20:39:56 -07:00
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} else if ((vaddr >= PROCESS_IMAGE_VADDR) && (vaddr < PROCESS_IMAGE_VADDR_END)) {
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*(T*)&g_exefs_code[vaddr - PROCESS_IMAGE_VADDR] = data;
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2014-04-29 20:16:12 -07:00
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2014-11-22 19:35:45 -08:00
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// FCRAM - linear heap
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2015-05-08 20:39:56 -07:00
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} else if ((vaddr >= LINEAR_HEAP_VADDR) && (vaddr < LINEAR_HEAP_VADDR_END)) {
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*(T*)&g_heap_linear[vaddr - LINEAR_HEAP_VADDR] = data;
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2014-04-17 18:05:34 -07:00
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// FCRAM - application heap
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2014-04-24 20:56:06 -07:00
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} else if ((vaddr >= HEAP_VADDR) && (vaddr < HEAP_VADDR_END)) {
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2014-12-02 22:13:29 -08:00
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*(T*)&g_heap[vaddr - HEAP_VADDR] = data;
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2014-04-03 19:04:50 -07:00
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2014-04-24 20:56:06 -07:00
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// Shared memory
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} else if ((vaddr >= SHARED_MEMORY_VADDR) && (vaddr < SHARED_MEMORY_VADDR_END)) {
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2014-12-02 22:13:29 -08:00
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*(T*)&g_shared_mem[vaddr - SHARED_MEMORY_VADDR] = data;
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2014-04-24 20:56:06 -07:00
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2014-04-25 22:27:25 -07:00
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// VRAM
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} else if ((vaddr >= VRAM_VADDR) && (vaddr < VRAM_VADDR_END)) {
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2014-12-02 22:13:29 -08:00
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*(T*)&g_vram[vaddr - VRAM_VADDR] = data;
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2014-04-25 22:27:25 -07:00
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2014-12-29 19:35:06 -08:00
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// DSP memory
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2015-05-08 20:39:56 -07:00
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} else if ((vaddr >= DSP_RAM_VADDR) && (vaddr < DSP_RAM_VADDR_END)) {
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*(T*)&g_dsp_mem[vaddr - DSP_RAM_VADDR] = data;
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2014-12-29 19:35:06 -08:00
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2014-05-06 20:32:04 -07:00
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//} else if ((vaddr & 0xFFFF0000) == 0x1FF80000) {
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2015-01-20 17:16:47 -08:00
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// ASSERT_MSG(MEMMAP, false, "umimplemented write to Configuration Memory");
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2014-05-06 20:32:04 -07:00
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//} else if ((vaddr & 0xFFFFF000) == 0x1FF81000) {
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2015-01-20 17:16:47 -08:00
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// ASSERT_MSG(MEMMAP, false, "umimplemented write to shared page");
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2014-08-02 16:46:47 -07:00
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2014-04-03 19:04:50 -07:00
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// Error out...
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2014-04-01 15:18:02 -07:00
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} else {
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2014-12-05 17:53:49 -08:00
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LOG_ERROR(HW_Memory, "unknown Write%lu 0x%08X @ 0x%08X", sizeof(data) * 8, (u32)data, vaddr);
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2014-04-01 15:18:02 -07:00
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}
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2013-09-18 20:52:51 -07:00
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}
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2014-08-28 11:20:55 -07:00
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u8 *GetPointer(const VAddr vaddr) {
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2014-05-07 18:04:55 -07:00
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// Kernel memory command buffer
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2015-05-08 20:39:56 -07:00
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if (vaddr >= TLS_AREA_VADDR && vaddr < TLS_AREA_VADDR_END) {
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return g_tls_mem + (vaddr - TLS_AREA_VADDR);
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2014-05-07 18:04:55 -07:00
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2014-04-29 20:16:12 -07:00
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// ExeFS:/.code is loaded here
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2015-05-08 20:39:56 -07:00
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} else if ((vaddr >= PROCESS_IMAGE_VADDR) && (vaddr < PROCESS_IMAGE_VADDR_END)) {
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return g_exefs_code + (vaddr - PROCESS_IMAGE_VADDR);
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2014-04-29 20:16:12 -07:00
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2014-11-22 19:35:45 -08:00
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// FCRAM - linear heap
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2015-05-08 20:39:56 -07:00
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} else if ((vaddr >= LINEAR_HEAP_VADDR) && (vaddr < LINEAR_HEAP_VADDR_END)) {
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return g_heap_linear + (vaddr - LINEAR_HEAP_VADDR);
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2014-04-17 18:15:40 -07:00
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2014-04-17 18:05:34 -07:00
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// FCRAM - application heap
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2014-04-17 18:40:42 -07:00
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} else if ((vaddr >= HEAP_VADDR) && (vaddr < HEAP_VADDR_END)) {
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2014-12-02 22:13:29 -08:00
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return g_heap + (vaddr - HEAP_VADDR);
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2014-04-17 15:40:42 -07:00
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2014-04-24 20:56:06 -07:00
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// Shared memory
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2014-05-15 15:56:28 -07:00
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} else if ((vaddr >= SHARED_MEMORY_VADDR) && (vaddr < SHARED_MEMORY_VADDR_END)) {
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2014-12-02 22:13:29 -08:00
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return g_shared_mem + (vaddr - SHARED_MEMORY_VADDR);
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2014-04-24 20:56:06 -07:00
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2014-04-25 22:27:25 -07:00
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// VRAM
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2014-07-22 19:38:21 -07:00
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} else if ((vaddr >= VRAM_VADDR) && (vaddr < VRAM_VADDR_END)) {
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2014-12-02 22:13:29 -08:00
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return g_vram + (vaddr - VRAM_VADDR);
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2014-04-25 22:27:25 -07:00
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2014-04-06 19:56:08 -07:00
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} else {
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2014-12-05 17:53:49 -08:00
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LOG_ERROR(HW_Memory, "unknown GetPointer @ 0x%08x", vaddr);
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2014-04-01 15:18:02 -07:00
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return 0;
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}
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2014-03-25 07:50:34 -07:00
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}
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2014-04-24 19:32:26 -07:00
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u32 MapBlock_Heap(u32 size, u32 operation, u32 permissions) {
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MemoryBlock block;
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2014-08-02 16:46:47 -07:00
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2014-04-24 19:32:26 -07:00
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block.base_address = HEAP_VADDR;
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block.size = size;
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block.operation = operation;
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block.permissions = permissions;
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2014-08-02 16:46:47 -07:00
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2014-11-18 05:48:11 -08:00
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if (heap_map.size() > 0) {
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const MemoryBlock last_block = heap_map.rbegin()->second;
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2014-04-24 19:32:26 -07:00
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block.address = last_block.address + last_block.size;
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}
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2014-11-18 05:48:11 -08:00
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heap_map[block.GetVirtualAddress()] = block;
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2014-04-24 19:32:26 -07:00
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return block.GetVirtualAddress();
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}
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2014-11-22 19:35:45 -08:00
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u32 MapBlock_HeapLinear(u32 size, u32 operation, u32 permissions) {
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2014-04-24 19:32:26 -07:00
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MemoryBlock block;
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2014-08-02 16:46:47 -07:00
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2015-05-08 20:39:56 -07:00
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block.base_address = LINEAR_HEAP_VADDR;
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2014-04-17 20:05:31 -07:00
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block.size = size;
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block.operation = operation;
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block.permissions = permissions;
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2014-08-02 16:46:47 -07:00
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2014-11-22 19:35:45 -08:00
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if (heap_linear_map.size() > 0) {
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const MemoryBlock last_block = heap_linear_map.rbegin()->second;
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2014-04-17 20:05:31 -07:00
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block.address = last_block.address + last_block.size;
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}
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2014-11-22 19:35:45 -08:00
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heap_linear_map[block.GetVirtualAddress()] = block;
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2014-04-17 20:05:31 -07:00
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return block.GetVirtualAddress();
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}
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2015-04-27 18:59:06 -07:00
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void MemBlock_Init() {
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}
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void MemBlock_Shutdown() {
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heap_map.clear();
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heap_linear_map.clear();
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}
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2014-08-28 11:20:55 -07:00
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u8 Read8(const VAddr addr) {
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2014-07-24 16:46:10 -07:00
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u8 data = 0;
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Read<u8>(data, addr);
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2014-08-28 11:20:55 -07:00
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return data;
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2013-09-18 20:52:51 -07:00
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}
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2014-08-28 11:20:55 -07:00
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u16 Read16(const VAddr addr) {
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2014-07-24 16:46:10 -07:00
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u16_le data = 0;
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Read<u16_le>(data, addr);
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2015-05-12 14:17:04 -07:00
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return data;
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2013-09-18 20:52:51 -07:00
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}
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2014-08-28 11:20:55 -07:00
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u32 Read32(const VAddr addr) {
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2014-07-24 16:46:10 -07:00
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u32_le data = 0;
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Read<u32_le>(data, addr);
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2015-05-12 14:17:04 -07:00
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return data;
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2013-09-18 20:52:51 -07:00
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}
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2015-03-11 13:10:14 -07:00
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u64 Read64(const VAddr addr) {
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|
|
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u64_le data = 0;
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|
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Read<u64_le>(data, addr);
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2015-05-12 14:17:04 -07:00
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return data;
|
2013-09-18 20:52:51 -07:00
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}
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2014-08-28 11:20:55 -07:00
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void Write8(const VAddr addr, const u8 data) {
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2014-07-04 20:46:16 -07:00
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Write<u8>(addr, data);
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2013-09-18 20:52:51 -07:00
|
|
|
}
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|
|
2014-08-28 11:20:55 -07:00
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|
|
void Write16(const VAddr addr, const u16 data) {
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2014-07-04 20:46:16 -07:00
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|
|
Write<u16_le>(addr, data);
|
2013-09-18 20:52:51 -07:00
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|
}
|
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|
|
|
2014-08-28 11:20:55 -07:00
|
|
|
void Write32(const VAddr addr, const u32 data) {
|
2014-07-04 20:46:16 -07:00
|
|
|
Write<u32_le>(addr, data);
|
2013-09-18 20:52:51 -07:00
|
|
|
}
|
|
|
|
|
2014-08-28 11:20:55 -07:00
|
|
|
void Write64(const VAddr addr, const u64 data) {
|
2014-07-04 20:46:16 -07:00
|
|
|
Write<u64_le>(addr, data);
|
2013-09-18 20:52:51 -07:00
|
|
|
}
|
|
|
|
|
2014-08-28 11:20:55 -07:00
|
|
|
void WriteBlock(const VAddr addr, const u8* data, const size_t size) {
|
2014-09-28 08:30:29 -07:00
|
|
|
u32 offset = 0;
|
2014-08-17 11:23:54 -07:00
|
|
|
while (offset < (size & ~3)) {
|
|
|
|
Write32(addr + offset, *(u32*)&data[offset]);
|
|
|
|
offset += 4;
|
|
|
|
}
|
2014-06-24 15:51:31 -07:00
|
|
|
|
2014-08-17 11:23:54 -07:00
|
|
|
if (size & 2) {
|
|
|
|
Write16(addr + offset, *(u16*)&data[offset]);
|
|
|
|
offset += 2;
|
|
|
|
}
|
2014-06-24 15:51:31 -07:00
|
|
|
|
|
|
|
if (size & 1)
|
|
|
|
Write8(addr + offset, data[offset]);
|
|
|
|
}
|
|
|
|
|
2013-09-18 20:52:51 -07:00
|
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|
} // namespace
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