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Rasterizer: Setup skeleton for Host Conditional rendering
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3630bfaef3
commit
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@ -16,7 +16,6 @@
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#include "video_core/rasterizer_interface.h"
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#include "video_core/textures/texture.h"
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namespace Tegra::Engines {
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using VideoCore::QueryType;
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@ -538,13 +537,17 @@ void Maxwell3D::ProcessQueryGet() {
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void Maxwell3D::ProcessQueryCondition() {
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const GPUVAddr condition_address{regs.render_enable.Address()};
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switch (regs.render_enable_override) {
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case Regs::RenderEnable::Override::AlwaysRender:
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case Regs::RenderEnable::Override::AlwaysRender: {
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execute_on = true;
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break;
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case Regs::RenderEnable::Override::NeverRender:
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execute_on = false;
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break;
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case Regs::RenderEnable::Override::UseRenderEnable:
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case Regs::RenderEnable::Override::UseRenderEnable: {
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if (rasterizer->AccelerateConditionalRendering()) {
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execute_on = true;
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return;
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}
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switch (regs.render_enable.mode) {
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case Regs::RenderEnable::Mode::True: {
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execute_on = true;
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@ -582,6 +585,8 @@ void Maxwell3D::ProcessQueryCondition() {
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}
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break;
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}
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}
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}
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}
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void Maxwell3D::ProcessCounterReset() {
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@ -618,7 +623,8 @@ std::optional<u64> Maxwell3D::GetQueryResult() {
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}
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void Maxwell3D::ProcessCBBind(size_t stage_index) {
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// Bind the buffer currently in CB_ADDRESS to the specified index in the desired shader stage.
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// Bind the buffer currently in CB_ADDRESS to the specified index in the desired shader
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// stage.
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const auto& bind_data = regs.bind_groups[stage_index];
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auto& buffer = state.shader_stages[stage_index].const_buffers[bind_data.shader_slot];
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buffer.enabled = bind_data.valid.Value() != 0;
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@ -127,6 +127,10 @@ public:
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/// Notify rasterizer that a frame is about to finish
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virtual void TickFrame() = 0;
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virtual bool AccelerateConditionalRendering() {
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return false;
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}
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/// Attempt to use a faster method to perform a surface copy
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[[nodiscard]] virtual bool AccelerateSurfaceCopy(
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const Tegra::Engines::Fermi2D::Surface& src, const Tegra::Engines::Fermi2D::Surface& dst,
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@ -525,6 +525,21 @@ void RasterizerOpenGL::TickFrame() {
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}
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}
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bool RasterizerOpenGL::AccelerateConditionalRendering() {
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if (Settings::IsGPULevelHigh()) {
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// Reimplement Host conditional rendering.
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return false;
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}
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// Medium / Low Hack: stub any checks on queries writen into the buffer cache.
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const GPUVAddr condition_address{maxwell3d->regs.render_enable.Address()};
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Maxwell::ReportSemaphore::Compare cmp;
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if (gpu_memory->IsMemoryDirty(condition_address, sizeof(cmp),
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VideoCommon::CacheType::BufferCache)) {
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return true;
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}
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return false;
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}
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bool RasterizerOpenGL::AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Surface& src,
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const Tegra::Engines::Fermi2D::Surface& dst,
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const Tegra::Engines::Fermi2D::Config& copy_config) {
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@ -100,6 +100,7 @@ public:
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void TiledCacheBarrier() override;
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void FlushCommands() override;
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void TickFrame() override;
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bool AccelerateConditionalRendering() override;
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bool AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Surface& src,
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const Tegra::Engines::Fermi2D::Surface& dst,
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const Tegra::Engines::Fermi2D::Config& copy_config) override;
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@ -600,6 +600,21 @@ void RasterizerVulkan::TickFrame() {
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}
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}
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bool RasterizerVulkan::AccelerateConditionalRendering() {
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if (Settings::IsGPULevelHigh()) {
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// TODO(Blinkhawk): Reimplement Host conditional rendering.
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return false;
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}
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// Medium / Low Hack: stub any checks on queries writen into the buffer cache.
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const GPUVAddr condition_address{maxwell3d->regs.render_enable.Address()};
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Maxwell::ReportSemaphore::Compare cmp;
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if (gpu_memory->IsMemoryDirty(condition_address, sizeof(cmp),
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VideoCommon::CacheType::BufferCache)) {
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return true;
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}
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return false;
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}
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bool RasterizerVulkan::AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Surface& src,
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const Tegra::Engines::Fermi2D::Surface& dst,
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const Tegra::Engines::Fermi2D::Config& copy_config) {
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@ -995,7 +1010,8 @@ void RasterizerVulkan::UpdateDepthBiasEnable(Tegra::Engines::Maxwell3D::Regs& re
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};
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const u32 topology_index = static_cast<u32>(maxwell3d->draw_manager->GetDrawState().topology);
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const u32 enable = enabled_lut[POLYGON_OFFSET_ENABLE_LUT[topology_index]];
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scheduler.Record([enable](vk::CommandBuffer cmdbuf) { cmdbuf.SetDepthBiasEnableEXT(enable != 0); });
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scheduler.Record(
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[enable](vk::CommandBuffer cmdbuf) { cmdbuf.SetDepthBiasEnableEXT(enable != 0); });
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}
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void RasterizerVulkan::UpdateLogicOpEnable(Tegra::Engines::Maxwell3D::Regs& regs) {
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@ -1012,11 +1028,11 @@ void RasterizerVulkan::UpdateDepthClampEnable(Tegra::Engines::Maxwell3D::Regs& r
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return;
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}
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bool is_enabled = !(regs.viewport_clip_control.geometry_clip ==
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Maxwell::ViewportClipControl::GeometryClip::Passthrough ||
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regs.viewport_clip_control.geometry_clip ==
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Maxwell::ViewportClipControl::GeometryClip::FrustumXYZ ||
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regs.viewport_clip_control.geometry_clip ==
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Maxwell::ViewportClipControl::GeometryClip::FrustumZ);
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Maxwell::ViewportClipControl::GeometryClip::Passthrough ||
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regs.viewport_clip_control.geometry_clip ==
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Maxwell::ViewportClipControl::GeometryClip::FrustumXYZ ||
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regs.viewport_clip_control.geometry_clip ==
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Maxwell::ViewportClipControl::GeometryClip::FrustumZ);
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scheduler.Record(
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[is_enabled](vk::CommandBuffer cmdbuf) { cmdbuf.SetDepthClampEnableEXT(is_enabled); });
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}
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@ -96,6 +96,7 @@ public:
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void TiledCacheBarrier() override;
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void FlushCommands() override;
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void TickFrame() override;
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bool AccelerateConditionalRendering() override;
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bool AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Surface& src,
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const Tegra::Engines::Fermi2D::Surface& dst,
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const Tegra::Engines::Fermi2D::Config& copy_config) override;
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