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https://github.com/yuzu-emu/yuzu-android
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shader_recompiler: Fix IADD3 input partitioning
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@ -42,14 +42,10 @@ enum class Half : u64 {
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}
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}
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void IADD3(TranslatorVisitor& v, u64 insn, IR::U32 op_b, IR::U32 op_c) {
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void IADD3(TranslatorVisitor& v, u64 insn, IR::U32 op_a, IR::U32 op_b, IR::U32 op_c) {
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union {
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u64 insn;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> src_a;
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BitField<31, 2, Half> half_c;
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BitField<33, 2, Half> half_b;
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BitField<35, 2, Half> half_a;
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BitField<37, 2, Shift> shift;
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BitField<47, 1, u64> cc;
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BitField<48, 1, u64> x;
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@ -58,11 +54,6 @@ void IADD3(TranslatorVisitor& v, u64 insn, IR::U32 op_b, IR::U32 op_c) {
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BitField<51, 1, u64> neg_a;
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} iadd3{insn};
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IR::U32 op_a{v.X(iadd3.src_a)};
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op_a = IntegerHalf(v.ir, op_a, iadd3.half_a);
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op_b = IntegerHalf(v.ir, op_b, iadd3.half_b);
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op_c = IntegerHalf(v.ir, op_c, iadd3.half_c);
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if (iadd3.neg_a != 0) {
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op_a = v.ir.INeg(op_a);
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}
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@ -72,7 +63,6 @@ void IADD3(TranslatorVisitor& v, u64 insn, IR::U32 op_b, IR::U32 op_c) {
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if (iadd3.neg_c != 0) {
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op_c = v.ir.INeg(op_c);
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}
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IR::U32 lhs_1{v.ir.IAdd(op_a, op_b)};
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if (iadd3.x != 0) {
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const IR::U32 carry{v.ir.Select(v.ir.GetCFlag(), v.ir.Imm32(1), v.ir.Imm32(0))};
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@ -97,15 +87,24 @@ void IADD3(TranslatorVisitor& v, u64 insn, IR::U32 op_b, IR::U32 op_c) {
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} // Anonymous namespace
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void TranslatorVisitor::IADD3_reg(u64 insn) {
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IADD3(*this, insn, GetReg20(insn), GetReg39(insn));
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union {
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u64 insn;
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BitField<35, 2, Half> half_a;
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BitField<31, 2, Half> half_c;
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BitField<33, 2, Half> half_b;
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} iadd3{insn};
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const auto op_a{IntegerHalf(ir, GetReg8(insn), iadd3.half_a)};
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const auto op_b{IntegerHalf(ir, GetReg20(insn), iadd3.half_b)};
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const auto op_c{IntegerHalf(ir, GetReg39(insn), iadd3.half_c)};
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IADD3(*this, insn, op_a, op_b, op_c);
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}
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void TranslatorVisitor::IADD3_cbuf(u64 insn) {
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IADD3(*this, insn, GetCbuf(insn), GetReg39(insn));
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IADD3(*this, insn, GetReg8(insn), GetCbuf(insn), GetReg39(insn));
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}
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void TranslatorVisitor::IADD3_imm(u64 insn) {
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IADD3(*this, insn, GetImm20(insn), GetReg39(insn));
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IADD3(*this, insn, GetReg8(insn), GetImm20(insn), GetReg39(insn));
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}
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} // namespace Shader::Maxwell
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